Reduce Flip-Chip Design Time with Cadence Advanced Package Router (APR) for 16.6 APD and SiP Layout

Perhaps the most time-consuming aspect to designing the package substrate for a large, high pin count flip-chip comes in the form of package routing. Escaping from underneath the flip-chip die itself, routing through multiple substrate layers, and finally connecting to the assigned BGA balls might easily account for 75% or more of the time spent on the substrate layout. Add the optimization of the routing to meet timing and SI constraints, and that percentage climbs even higher. It is with this in...(read more)