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Reduce Flip-Chip Design Time with Cadence Advanced Package Router (APR) for...
Perhaps the most time-consuming aspect to designing the package substrate for a large, high pin count flip-chip comes in the form of package routing. Escaping from underneath the flip-chip die itself,...
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ISQED Keynote: How RTL Synthesis Must Change for Advanced Node Designs
Think RTL synthesis is a solved problem that needs no further discussion? Think again. In a keynote speech at the recent International Symposium on the Quality of Electronic Design (ISQED 2013) Sanjiv...
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SKILL for the Skilled: Many Ways to Sum a List (Part 7)
In this episode of SKILL for the Skilled I'll introduce a feature of the let primitive that Scheme programmers will find familiar, but other readers may have never seen before. The feature is called...
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What's Good About PCB SI and Vias? 16.6 Has Many New Enhancements!
In the Allegro PCB SI 16.6 release, vias in SigXp have been enhanced to make it more efficient for design use. In addition, Allegro PCB Editor padstacks will be used to build the models.Read on for...
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Incisive Debug Analyzer is a Finalist for EETimes and EDN ACE Software...
Great news.... Incisive Debug Analyzer (IDA) is one of five finalists for the EETimes/EDN Annual Creativity in Electronics (ACE) Awards in the Software Product of the Year category. In addition to IDA,...
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Five-Minute Tutorial: Set Flip-Chip Bumps as Voltage Sources in EPS/EDI Rail...
When running power and rail analysis for a flip chip, we used to have to spend some time creating the voltage sources. It wasn't too terrible; usually we would output the bumps into a Cadence Encounter...
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Engineer Video: Best Practices for Mixed-Signal SoC (MS-SoC) Verification
Why is there a need for "best practices" in mixed-signal SoC verification, and what are some of those practices? A presentation at the recent DVCon 2013 conference addressed these questions by showing...
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Unleashing Mixed-Signal Tech on Tours (ToTs) in North America
At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two days. Cadence customers including IBM, Texas Instruments, Maxim and Freescale shared their mixed-signal methodologies...
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Multi-Level Physical Hierarchical Flow – A New Approach for Giga-Scale ASIC...
A presentation at the DesignCon 2013 conference illustrated a new methodology that speeds timing closure for ASIC and SoC designs with hundreds of millions of gates. Called "multi-level physical...
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How Hardware/Software Co-Development Fuels “Product Creation”
I've written recently about "product creation," a concept that looks beyond the chip or board and considers the requirements of the entire end product, including hardware, software applications, and...
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What's Good About RF PCB and Autoplace? 16.6 Has Many New Enhancements!
The 16.6 Allegro RF PCB application has many new enhancements.I’ll cover a few over the next several weeks. Here are some major autoplace related enhancements:Grouping in Design Entry HDL...
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CDNLive Silicon Valley 2013 Proceedings Available for Download!
CDNLive Silicon Valley, held March 12-13, 2013, featured nearly 100 technical sessions from customers, partners, and Cadence R&D experts. Presentations from most of those sessions are now available...
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Develop for Debugability – Part 1
Debugging is the most time-critical activity of any verification engineer. Finding a bug is very often a combination of having a good hunch, experience, and the quality of testbench code that you need...
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Videos, Presentations Highlight Front-End IC Design Methodologies
Want to know how other designers are solving front-end IC design challenges, and what Cadence R&D is doing to help? The Front-End Design (FED) Technology Summit, held at Cadence San Jose...
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What's Good About Allegro PCB Editor Generic Cross-Section Files? See for...
Beginning with the Allegro PCB Editor 16.6 release, you are provided a methodology to export a technology (.tcf) or constraints (.dcf) file which is a generic cross-section. A generic-cross-section...
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Corral Your Selections with New Lasso and Path Modes in 16.6 APD and SiP
The level of ease and efficiency you experience in selecting the items needed for modifying in your substrate can mean the difference between a great design experience and an exercise in frustration...
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Virtuosity: 10 Things I Learned in March by Browsing Cadence Online Support
Topics in March include advanced analysis in ADE GXL, taking advantage of lots of features for doing statistical analysis in ADE XL, defining bindkeys in ADE L (yes, you can do that!), plus a variety...
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Video: A Unified Modeling Flow for Virtual Platforms and High-Level Synthesis
Can the same SystemC TLM2 models be used in virtual platforms and high-level synthesis? Today the answer is typically "no." However, there is a "middle ground" modeling methodology that can turn this...
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TSMC 2013 Symposium: Morris Chang Overviews Semiconductor Market, TSMC Progress
Morris Chang, founder, chairman and CEO of TSMC, has had a profound and lasting impact on the semiconductor industry - and when he speaks publicly, you know it comes with deep knowledge and insight....
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TSMC 2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies
The TSMC 2013 Technology Symposium, held April 9 in San Jose, California, brought good news for anyone interested in advanced node or 3D-IC technologies. Keynote speakers noted excellent yields and...
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