At CDNLive in Munich, Cadence's Robert Schweiger gave a walkthrough all of the things that Cadence is doing in automotive. Since Cadence's Virtuoso platform is a leader in analog design, Cadence has been in automotive semiconductor since the market has existed. But there is a new era. "You Can't Do ADAS with a Microcontroller" The dilemma is that on the one hand, government regulations are driving to reduced emissions, increased efficiency, lower power consumption, and lower weight. The EURO NCAP program wants enhanced safety (which things like lower weight work against), ADAS, Car2X communication, improved human interface. One change is that the old "one function per ECU" model doesn't work any longer, partially because the ECUs and their associated wiring are unnecessary weight, and partially because computational and network requirements are so much more complex with cameras/lidar/radar. Part of the solution is low-power, high-performance SoCs. But there is a culture clash in that the traditional car manufacturers and their OEMs have very limited experience of designing such SoCs, or even anything at all in those type of advanced processes. On the other hand, companies, such as mobile companies, have no experience of designing for automotive reliability. The foundries, and the EDA/IP ecosystem also have only limited experience, since nobody wanted to do advanced-node digital chips with automotive reliability before. This is leading to disruption in the traditional supply chain: Some OEMs and Tier 1s are doing SoCs Semis such as NVIDIA and Qualcomm are moving up the stack providing complete solutions New startups creating ADAS platforms, or components Another disrupter is deep learning and neural networks (NN). You can't do autonomous driving without AI. However, there are major challenges in moving NN from the cloud to the vehicle, but it has to be done since driving decisions can't tolerate latency and network unreliability and have to be done on-vehicle. Doing all this in constrained power and area is a challenge. Other new challenges are: Memory bandwidth requirements for computer vision and AI are orders of magnitude higher than "old" automotive semiconductors. Bandwidth and weight considerations require switching from old fashioned wiring harnesses to Ethernet. Functional safety, security, and reliability are all new challenges for everyone on SoCs on leading-edge processes. Nobody has done it before. System Design Enablement Cadence has introduced a concept that it calls System Design Enablement for this sort of holistic design, which has to take into account everything from software, through silicon, to package, reliability, and mechanical. The system cannot be optimized by taking each layer in isolation. What is implemented in software and implemented in silicon has major impact on system performance, power, and time to market, for example. Functional safety requires taking everything into account, so a connector failure might be addressed by software running on a special triple-redundant on-chip safety processor. There is no one right answer to all this, which is part of the message of SDE: for business reasons, systems will need to be differentiated in various ways and a vehicle built to a low-end price point might make different choices from a high-end premium marque. However, all the vehicles need to be safe and efficient. Below is an example of an ADAS SoC with the subsystem partitioning. Neural Network Processor The computational requirements for neural networks for vision seem to be 1 TMAC/s for semi-autonomous driving and 10 TMSC/sec or more for full autonomous driving. Cadence recently announced the Tensilica Vision C5 DSP for neural network processing, which is targeted specifically into this market. It is also designed to scale to multi-core and multi-processor systems. The datapoint that best positions this processor is that it does 1TMAC/s in under 1mm2 at 16nm. Cadence has been doing a lot of research in how to implement cloud-based neural networks efficiently in silicon for ADAS and autonomous driving. We have a superset NN called CactusNet, which can emulate other networks, and has a lot of control knobs that can be used to gradually reduce the system requirements while keeping the performance metric, such as recognition, up close to the limit. For more details on this, see my two posts CactusNet: One Network to Rule Them All and CactusNet: Moving Neural Nets from the Cloud to Embedded , and for details of the Vision C5 DSP, see my post Vision C5 DSP for Standalone Neural Network Processing . Memory Interfaces There are a number of memory interfaces targeted at different applications from hyperscale datacenter server processors to mobile phones. For automotive, the key is to deliver the very high bandwidth required with optimized cost, power, and reliability. Of the currently available interfaces, the one most suited to automotive applications is LPDDR4. It has become the de facto standard. It has 3200-4267 data rates, 12-17GB/s per die, so 24-34GB/s per package. Despite the LP (low power) designation, LPDDR4-4267 is actually faster than the maximum DDR4 standard rate. It achieves these rates at a low-power point due to low swing I/Os, easier frequency scaling, and databit inversion. This results in a 40% power reduction from regular (not LP) DDR4. It also has better signal integrity, and lower EM interference. That would be fine for mobile, but automotive needs more: DRAM vendors have committed to long-term supply (15 years) of LPDD4 DRAMs for automotive production and spares First with post-package repair Extended operating temperature range, especially for the high end of automotive range, which is a challenge for dynamic memory in general Temperature compensation Cadence has LPDDR4 interface IP and memory models. It also has Sigrity-ready silicon-accurate power-aware IBIS models, virtual reference designs, accurate package models, and more to enable systems to be designed and analyzed. For details, see the DDR IP page and the LPDDR4 Complete Solution page. Automotive Ethernet The future of networking in cars is Automotive Ethernet. This is not just regular Ethernet put into a vehicle, there are special requirements for automotive since there is both time-sensitive data, such as vehicle control, and lower priority data, such as rear-seet entertainment. The Ethernet standard has been enhanced with several variations for time-sensitive networking (TSN) so that Ethernet can deliver low-latency deterministic data transfers. The buzzwords (or, since this is Ethernet, the xx characters in the 802.xx standards) are: 802.1Qav (Traffic Shaping) and 801.2Qbv (Enhancements for scheduled traffic) 802.1Qbu/802.3br (Frame Pre-Emption) 802.1CB (Frame Replication and Elimination) 802.1Qci (Ingress Policing) The current automotive PHY in production is 100Mb/s which is low for cameras. Work is going on to push the PHY first to 2.5Gb/s and eventually 10Gb/s and perhaps 25Gb/s. There is also development going towards attaching optical fiber PHYs (for both plastic and glass fiber), since optical fiber is both lighter and immune to electrical interference, compared to copper. The Cadence Automotive Ethernet MAC IP also contains a range of active safety features that check for correct operation of both the MAC itself and how it is used, as illustrated in the diagram below: You don't have to take my word for it, or anyone at Cadence. The Gigabit Ethernet MAC is certified ASIL-B ready: Cadence has a family of IP products with 10/100/1G/2.5G MACs with TSN, 1588, and DMA. There is also verification IP (VIP) for Ethernet 10/100/1G/10G. For details see the Automotive Ethernet page . Tomorrow Tomorrow's post concludes Robert's presentation, looking at functional safety and reference platforms.![]()
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