Let’s assume that we are working on a PCI Express Gen 4 serial link, running at 16Gbps. Let’s also assume that we were able to obtain models for the AC coupling caps, packages, and connectors from your suppliers, as well as an IBIS-AMI model for your SerDes receiver. That leaves PCB traces and vias for the board to be eventually designed, and an IBIS-AMI model for your transmitter, which we will assume is currently unavailable from the supplier. Let’s first tackle the PCB structures. Pre-Layout Modeling of PCB Interconnect Modeling of the PCB traces can start out by obtaining the proposed stack-up, including the material, dielectric and conductor thicknesses, impedance, line width, and spacing for the serial link’s differential pair. Next, identify which layer the main routing for the serial link (typically adjacent to a ground plane) will be, so that you can generate a microstrip or stripline model as applicable. With that information in hand, the next step is to estimate the length of the interconnect. For that a “floorplan”, or rough placement of the PCB is useful. Floorplanning tools will enable you to enter a basic PCB outline, a stackup, allow you to place parts from your footprint library, and even define some simple nets, all without a formal design, completed schematic, or netlist. When looking at the floorplanning, don’t forget about the AC coupling caps. Will they be located on the top side of the board, where the SerDes devices typically reside, or will they be on the back side with most of the other discrete? This choice will result in different via configurations, so careful thought needs to be given at this point. Surface mount connectors also fall into this category, in the context of the overall system design. From the floorplan, find the Manhattan length of the serial link as your starting point for PCB length. Enter this information into your SI tool to generate a W-element model for the main PCB trace routing, and put this into your SI test-bench. Figure 1 – Taking Manhattan lengths from floorplan for pre-layout trace modeling Repeat this process for any other trace models needed for your testbench, including microstrip fanout traces, traces connected to either side of AC coupling caps, and so forth. With nominal PCB trace models in place, attention can be turned to vias. Vias are a critical part of double-digit, multi-gigabit serial links. They generally represent the biggest “speed bump” in the overall signal path, and designing them such that insertion and return losses are minimized, is crucial to successfully passing traffic at double-digit data rates. In some limited cases, it may be possible to eliminate vias with microstrip-only routing, but this is often not the case. The number of vias for high data rate serial links should certainly be minimized, but they typically cannot be eliminated. Figure 2 – The via discontinuity “speed bump” (figure courtesy of Tektronix) Drill diameter, pad size, antipad design, and proximity to ground vias are all critical items. A key consideration for vias is the stub length, or unused portion of the signal path through the via, which can lead to reflections in the channel. Via stub length can be controlled by careful selection of routing layer, utilization of blind vias, or backdrilling. Figure 3 – Optimizing via structure parameters Automated sweeping of these critical parameters can significantly accelerate the optimum via design for the serial link. Once the desired via structure is identified, it needs to be captured so that it can be implemented in the PCB layout. An automated mechanism for passing these via design parameters is very beneficial, as it ensures that they are implemented as intended in the physical layout, will be “correct by design”, and impact of the vias on final eye diagrams will be minimized. Next time > IBIS-AMI Modeling Author Biography Ken Willis is a Product Engineering Architect focusing on SI solutions at Cadence Design Systems . He has nearly 30 years of experience in the modeling, analysis, design, and fabrication of high-speed digital circuits.Prior to Cadence, Ken held engineering, technical marketing, and management positions with the Tyco Printed Circuit Group, Compaq Computers, Sirocco Systems, Sycamore Networks, and Sigrity . More about Signal Integrity: How to Address the Challenges of Serial Link Design and Analysis Why SerDes Signaling Is Trending Towards PAM Encoded Signals How to Build an IBIS-AMI Model (Video) Signal Integrity Methodology for Multi-Gigabit Serial Link Interfaces (1 of 7)![]()
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