I definitely had cognitive dissonance at the ARM foundry talks at TechCon. The first thing was that the organizer of the sessions was Kelvin Low. Since he was the marketing guy for Samsung Foundry until summer before joining Arm as their VP of marketing for physical libraries, it was odd to see him introduce Tom Quan of TSMC. Perhaps even more unusual was when Kelvin introduced Robert Stear of Intel Custom Foundry. I don't recall seeing Intel at TechCon ever before. There were three presentations by the foundries and their partners: Tom Quan of TSMC, along with Millind Mittal of Xilinx, Nick Heaton of Cadence, and Ravi Mahatme of Arm (which I will cover in a separate post) Robert Stear of ICF and Kiran Buli of Arm KK Lin of Samsung and Rupal Gandhi of Arm I asked Kelvin what happened to GlobalFoundries and he said it was just to hard to get everything organized, given he only came onboard a few months ago. Much of the schedule was already set in stone. Next year he promised to have GlobalFoundries, SMIC and more. I am going to focus on the process roadmaps of the three foundries, rather than go into a lot of details of exactly which libraries are available from Arm. The details will change, and I think can be summed up by saying that if processes are in production, Arm has a whole family available, and if it is at the stage of early PDKs or risk production, they probably have a limited offering. Intel Custom Foundry Robert Stear titled his talk Transforming the Mobile Markets . He puts them in the plural since Intel classifies them into the cutely named hero/mainstream at the high end, and entry/value at the low end. For all mobile products, the table stakes are performance, good power efficiency, ultra-low leakage (for long standby), small area, and ease of design. The high end is all FinFET (Intel seems to have given up calling them Trigate). Ath the low end it is ease-of-design and low cost. Their forecast is that the low end won't go to FinFET until 2020, and then only a little bit of the market because of cost. Intel has three process families for foundry: 14nm, 10nm, and 22FFL. The 14nm and 10nm processes are versions of the mainline Intel processes used for Intel products, but 22FFL is a sweet spot for the low end of the market: FinFET, but with 28nm planar pricing, partly due to single patterned metal. It now has a silicon validated IP portfolio, with Arm libraries and POP kits in development. Apparently, their partners say "it is the industry's easiest to use FinFET process." The comparison is that leakage is 1000X better than 28nm planer, 30% higher performance and 20% lower area. The roadmap goes to 22FFL+ (the PDK 0.5 has just been released) with 3Vts and two additional metal options. Then another version of the process, simply named 22FFL next gen since it doesn't have a real name yet, with finer contacted poly pitch (CPP), denser interconnect (presumably finer metal 2), and denser bitcell. The timelines are in the above chart. 22FFL is Q2 2018. 22FFL+ is Q4. 22FFL next gen is Q4 2019. Intel calls 10nm the most advanced technology being manufactured. To be fair, they are much more conservative than their competitors, and what they call 10nm is closer to what the foundry companies call 7nm. On the other hand, that means that when they say it is the best PPA 10nm process, you have to realize that is not entirely an honest comparison. For foundry, this process is in production this quarter (Q4 2017). There are two platforms GP (general purpose) and HPM (high performance mobile). It also has a 3 step roadmap, with 10 HPM/GP now, moving to 10HPM+/GP+ and then just add another plus sign (that last process is just in exploration right now, probably with an additional metal stack). The schedules are in the above chart. Not that they go out some way, and the 10++ processes are not scheduled for production until 2020. In August 2016 they announced Arm on Intel Custom Foundry at 10nm. It was a proof of concept, without a lot of optimization (no POP kits) with industry standard tools. RTL to tapeout was just 14 weeks. There were no process tweaks, and it got 3.3GHz at the latest signoff. I was surprised that Robert talked about a chip that Cadence, Intel and Arm are doing for a high-performance low-power optimized Cortex-A55 and a low-power A55 with DynamIQ and more. This is work in progress. Samsung Foundry Next up was KK Line of Samsung. He gave a brief history of Samsung foundry and the environment in which it operates. Back in the happy days of easy scaling there were 22 foundry companies on the leading edge. Now they are down to 4 (including Samsung, of course). Until this year, Samsung semiconductor was a memory business and a logic business, but now foundry has been broken out on its own as an independent business unit. That is the latest step on a journey that started in 2005 when Samsung enetered the foundry business. Today, the Austin fab (which I believe is the largest in the US) has been converted from memory to logic. So, as KK said, "all foundry can be build in the USA, which should please our president." There are two other fabs, S1 in Korea (the original logic fab) and S3, which is nearly complete, in Hwaeseong. As I'm sure you know, Samsung has a two-headed roadmap with FinFET and FD-SOI (or FDS as Samsung calls it). If you didn't know that, then see my post Samsung Foundry Forum: Roadmaps from earlier this summer when I reported on the Samsung Foundry Forum. Here is the roadmap. There is a huge amount of information on this one chart. The red at the top is FD-SOI and the blue at the bottom is FinFET. The latest nodes to be announced are 18FD-SOI and, at the Eureopean foundry forum, 8LPP (a derivative of 10nm with smart scaling). Except for 9nm, Samsung has nodes planned at every other number down to 4nm, some are "new" processes, such as 7nm, and some are shrinks of earlier nodes, such as 8nm which is a shrink of 10nm, and 11nm which is a shrkink of 14nm. Risk production for 8nm starts in Q4. The 7nm node is the first EUV node. The PDKs are ready. They are forecasting 4nm in 2020 (which was already announced) with gate-all-around (GAA). One data point is that EUV is on-track to have 250W source power, which has always been a requirement from the foundries to be able to use EUV in HVM. Not only does it make for a lower cost process due to fewer masks, but design is a lot simpler since RC variation is a lot lower, and there is none of the coloring associated with the extra masks either. They also have announced the world's first 28FDS eMRAM test chip, see the bottom right of the above chart. This technology will also be moved to the 18FDS node. More Information As usual with the foundries, there really isn't any more information. At events like this, they present roadmaps and data, but generally there is only the most high level information on their websites. So this is it, I'm afraid. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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