Foundry Roadmaps: Intel, Samsung
I definitely had cognitive dissonance at the ARM foundry talks at TechCon. The first thing was that the organizer of the sessions was Kelvin Low. Since he was the marketing guy for Samsung Foundry...
View ArticleDealing with AOCVs in SRAMs
Systems on Chip, or SoCs as they’re more commonly called, have become increasingly more complex, and incorporate a dizzying array of functionality to keep up with the evolving trends of technology....
View ArticleWould You Let Your Child Ride in an Autonomous Car?
DVCon is one of the premier conferences WW for design and verification. The DVCon India show has grown significantly over the last 4 years of its existence and this year’s edition was as vibrant as...
View ArticleCASPA Fuses AI and Semiconductor
CASPA is the Chinese American Semiconductor Professional Association. Once a year they have their annual conference and dinner banquet. I ended up getting involved with them a few years ago when I...
View ArticleCadence Academic Network Lead Institutions
Introduction Many suggestions were spinning around the globe, many ideas are being presented, many meetings are being made about how to strengthen customer relationship with the company, how to make...
View ArticleThe Alto: The Machine That Changed the World
The Machine That Changed the World is actually the title of a well-known book about the history of Toyota's lean manufacturing and the importance of the automobile industry (and is fascinating in its...
View ArticleWhat's For Breakfast? Video Preview November 27th to December 1st 2017
https://youtu.be/AMMOBeri5E8 Coming from building 10 fussball table (camera Sean) Monday: What's the Difference Between MOESI and MESI? Cache-Coherence for Poets Tuesday: CCIX Update: TSMC, Xilinx,...
View ArticleHow Can I Assess Process Variation in My IC Package Design?
In a previous blog we talked about the IC Packaging Design Variant tool. As you recall, this tool extended and eased the practice of a designer creating one database that represented multiple...
View ArticleVirtuosity: Organizing Waveform Families
When plotting waveforms in Virtuoso Visualization and Analysis across sweeps you might want to group plots with the same values together, or display each corner in the same color etc. Of course, you...
View ArticleThe Alto—Forty Years On
I talked yesterday about the history of the Xerox PARC Alto machine, which is a computer from the 1970s that is still influencing your smartphone today. On December 10th, forty years to the day after...
View ArticleWill Artificial Intelligence Take Over Art Forms?
In February last year, San Francisco’s art lovers were treated to a new kind of exhibition. Titled, “DeepDream: The Art of Neural Networks” and held in the trendy Mission District, the art on display...
View ArticleA Peek into the Future of Signal Integrity with Artificial Neural Networks
Imagine how great life could be if computers or robots can do all our tedious work and we get to enjoy life and work on the things that are meaningful to us, i.e. the first figure on our left. These...
View ArticleWhat You See Isn't Always What You Get
I wrote earlier in the week, in my post The Alto—Forty Years On , about the origin of the term WYSIWYG (pronounced whizzy-wig if you didn't already know). Today, it's the day before a break so I...
View ArticleCadence Modus DFT at International Test Conference 2017
While DAC is the focal point for the EDA industry, the test community travels in a slightly separate orbit. There are many conferences throughout the year, and around the globe, to help bridge the...
View ArticleWhat's the Difference Between MOESI and MESI? Cache-Coherence for Poets
Increasingly, a lot of SOCs contain multicore processors, multiple separate processors, accelerators, and high-performance DMA devices. They also have cache memories, memories local to a block or core,...
View Article26262 4U: Infineon and the Incisive Functional Safety Simulator
Infineon and Cadence have a bit of a history: they’ve been working together on functional safety mechanisms for around two and a half years now, and Infineon has been using the entire Cadence...
View ArticleA Cadence Carol
I took my son to the Dickens Fair near San Francisco last weekend. We dressed up in our favorite Victorian garb—my son looked like he stepped right out of a Dickens novel. People thought he really...
View ArticleWhat's For Breakfast? Video Preview December 4th to 8th 2017
https://youtu.be/LcmP8GkqvEw Coming from outside on the Cadence campus (camera Sean) Monday: JUG: Formal Verification Signoff Tuesday: Supercomputers Wednesday: Advanced Packaging Delivers More than...
View ArticleCCIX Update: TSMC, Xilinx, Cadence, Arm...and Jasper
CCIX (pronounced see-six) is the Cache Coherent Interconnect for Accelerators. I wrote about it in my post CCIX is Pronounced C6 and also when Cadence announced its collaboration with TSMC, Arm and...
View ArticleWhiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 1
In this week's Whiteboard Wednesday, Tom Hackett explains neural network basics using an Excel spreadsheet as a learning vehicle. You can download the spreadsheet here:...
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