It’s now official: Perspec System Verifier is rated the #1 product in the #1 category of Portable Stimulus, according to the 2017 EDA User Survey published on Deepchip.com . There were 33 user responses in favor of Perspec as the #1 tool, and driving Portable Stimulus into the #1 EDA tool category. They wrote 3,097 words describing their thoughts and opinions on what they liked about Perspec. “What most users liked about Perspec was the payoff they got with it after the initial ramp-up. Big ‘likes’ for its ARM libs, its coverage-driven pattern generation, and of course stimulus reuse across derivative SoCs and through all the stages of SoC development.” John Cooley, Deepchip.com Selected User Comments “We have been using Cadence Perspec for a while now. We use it to reuse stimulus across all our derived chips from a base chip, and reuse our stimulus across platforms. We currently use it with Incisive and Protium.” “With it our early IP guys can talk to our SoC guys, who can talk to our functional verif. guys, who can talk to our post-silicon verif. guys. Its automated test generation based on the formal declaration of *action* is great for complex system level tests -- which would not be possible to create manually.” “Perspec's coverage-driven pattern generation allowed us to create scenarios that we would not have created manually, due to their complexity.” User Comments about Perspec The most commonly mentioned reasons users prefer and voted for Perspec include: Saved a lot of time creating and maintaining lots of SoC tests Ease of modeling First to demonstrate multi-processor capabilities Ease of describing and visualizing complex high-level test intent Tests are less prone to coding errors, typos, etc. And are more readable Fast constraint solvers enable more flexible modeling and reuseability Contribution by every job function (IP creator, architect, and other domain experts) Integrated debugging of lengthy portable stimulus and design activity in Indago Integrated coverage solution with vManager Comprehensive coherency, power, and DVM library for Arm CPU sub-systems Reuse from IP to SoC and software level Reuse the tests from RTL and gate Incisive simulations, and Palladium and Protium, and silicon Generates tests in C or SystemVerilog Cadence Innovations are the Basis for Accellera Portable Stimulus Specification There is one topic that users are still coming to understand, and the current confusion can be found in some of the user comments. When Cadence developed Perspec we defined a system level notation (SLN) language that is used to model the SoC and SW under test and the scenarios that define the generation of portable tests. This language was enhanced while working with some of the most demanding users in the industry over the course of several years of industrial application. When Accellera formed the Portable Stimulus Working Group (PSWG) , Cadence chose to donate SLN, and most of the resulting PSS v1.0 draft specification is based on SLN concepts. Even after the changes introduced via the standardization process, even a casual observer can see the roots of SLN in PSS examples when held next to each other. The expression of PSS in either its DSL or C++ syntax can also be traced to the SLN contribution baseline. We plan for Perspec to support both syntaxes of PSS shortly after the standard is officially ratified, and will continue to support SLN. Users will be able to use any of the syntaxes and mix them as desired, to provide maximum reuse. For more information, including how PSS can address your specific needs (low-power, coherency, memory virtualization, multi-IP scenarios, or interconnect testing), contact pss_info@cadence.com .![]()
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