How important is it for your advanced node products to get early silicon learning? How are your test chips compared to real products? Some answers are provided below in short summary from the “Methodology for Analyzing and Quantifying Design Style Changes and Complexity using Topological Patterns” presentation that Jason Cain, Principal Member of the Technical Staff with AMD gave at the SPIE conference. Fabless design companies spend a lot of effort to try to acquire as much and as fast as possible silicon learning to maximize successful production ramp-up. The main acquisition of silicon learning is through test chips using different types of design styles such as standard cells, macros, routing layers, and so forth. One of the key questions that is hard to answer is how representative of a real product is the layout of a test chip. This type of topological analysis requires two basic capabilities. First is a methodology for analyzing the “pattern” space of a layout: namely to measure the types and quantities of patterns that are being used in a design, including with a metric for pattern complexity. Second is the ability to compare, identify the difference and track what has changed between the test chip and the product designs to identify the “new pattern” space. Cadence Diffing aNd Analytics flow (DNA) based on Cadence Pattern Analysis introduces a novel methodology for full chip high performance topological pattern analysis that can be used to analyze design styles in order to quantify and measure design changes and the degree of layout regularization. This new Design For Manufacturing (DFM) methodology has a pattern capture phase where a full analysis of the “known pattern” space is performed to build a database of all known patterns along with corresponding metadata, such as dimensions and pattern relationships. This new approach allows engineers to perform a full profiling across all patterns that exist in design and without needing to explicitly specify what patterns to analyze. For instance, it can be applied to the test chip layout database. In the pattern compare phase, a new design can be compared to this pattern database to identify the “new pattern” space. With the Cadence DNA flow, fabless companies can measure the actual test chip coverage of their real products and learn from this analysis what to include in the next generation test chip. In addition, new patterns found in the product layout can be scored by complexity. The most complex new patterns are potential new yield detractors and can be sent for further analysis and inspection to the foundry teams, for early silicon learning. As a result of this early proactive silicon learning, designers can use pattern-based layout optimization to remove these yield limiters from their designs and maximize their chance of fast production ramp-up. For more information, you can check the full article Methodology for analyzing and quantifying design style changes and complexity using topological patterns. If you would like to discuss this topic feel free to send a message at spie2017@cadence.com or please visit us at SPIE 2018 in San Jose, Ca in March.![]()
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