At IEDM in December, I sat down with Gary Patton, CTO of GLOBALFOUNDRIES, to discuss their manufacturing in general, and especially their 7nm process, EUV, and their Malta fab8, where Gary is based. We actually met the day before the presentation at IEDM of their process by Basanth Jagannathan. I'd read the paper in the proceedings to prepare, and then I got a personal presentation from Gary himself. Gary Patton Gary ran through the recent process history of GLOBALFOUNDRIES. From now on I'll just say GF. I don't know who decided that their corporate policy would be that, in addition to having a very long name, that name should always be in all upper case, but it was a poor decision. It makes any writing containing the company name hard to read since your eye is always drawn to the ENORMOUSLOGO. GF has two process families, FD-SOI and FinFET. FD-SOI is targeted at battery powered devices where power is more important than performance. FinFET is targeted at high-performance computing (HPC). The basic FD-SOI process was licensed at 28nm from ST Microelectronics who developed it (for the history of that see my post Silicon on Nothing: The Origins of FD-SOI) . However, they never offered that process since their market research showed that people wanted a faster process (they did have a 28nm planar process). So they developed their own next-generation version of the process 22FDX. Process naming is an inexact science—nothing on a 14nm process is actually 14nm, for example. However, by unspoken agreement, 22nm means most layers are kept to a pitch of 80nm, meaning that with aggressive OPC 193nm immersion lithography, and off-axis illumination, it can be manufactured without double patterning. This is key to keeping the cost down. For the FinFET family, GF's internal development was proceeding too slowly and so they licensed Samsung's 14nm process, 14LPP. This has been in volume manufacturing at their Malta (upstate New York) fab 8. Of course, a process needs more than just a single node, it needs a roadmap. For the FD-SOI side of the house, GF announced 12FDX. For the FinFETs, they announced 12LP (which I believe is an optical shrink of 14LPP with the same design rules but better power/performance). They announced that they would skip any intermediate processes and go straight to 7nm with 7LP. This process is the one that they announced in detail in two papers during IEDM, one explicitly on the process, and hidden away in the session on copper interconnect was another paper on fully-aligned via ("fully-aligned" meaning that the via was aligned on the copper lines of both interconnect layers, and so there would never be a via that only partially overlapped one of them, leading to a bad worst-case resistance). In addition to a process, there is a range of IP, such as memories and Ethernet. The HSS (high-speed SerDes) is 60G, with 112G on the way. Given that GF struggled to develop their own 14nm process, how could they realistically expect to do 7nm? Two things made it possible. The first was simply that they had been running 14nm in high-volume, and so had built up experience at running a state-of-the-art process, requiring extensive double patterning, at 300mm in high volume. More importantly, IBM sold their semiconductor business to GF, including a lot of their process people (who are known as TD in the industry, for technology development). In fact, Gary himself had been at IBM. He was offered the choice of remaining at IBM and continuing to head up their semiconductor R&D, but he decided to take the challenge of doing his part in building a world-class foundry. Of course, Gary is proud at what GF have achieved on his watch, delivering 14LPP, developing 12LP, and now most of the way through developing 7LP with risk production due to start in the middle of next year. The comment on the right in the above slide is a little bit of marketing. Malta is, indeed, the most advanced pure-play foundry in the US, because Samsung and Intel are not pure-play foundries. In fact, GF are the only pure-play foundry in the US. As he said to me in our interview: People used to say there were only 3 leading edge [non-memory] semiconductor companies. Now they say there are 4. GF and IBM I asked Gary about the fact that the paper I had seen on copper vias was from IBM. He said that he is very impressed with IBM's semiconductor strategy over the years. In order to be the leaders of the mainframe market, they needed to manufacture their own semiconductors on their own process. In the beginning, they had their own fabs and that is just what they did. But servers are not a high volume market and at some point they didn't fill a fab. If you know anything about semiconductor manufacturing, you know that "fill the fab" is an imperative, since most of the cost comes from depreciation whether you build anything or not (a modern fab depreciates at around $20-40 per second). So the next step for IBM was to enter the ASIC business to have other designs to run in the rest of the capacity that they didn't use for their own needs. However, ASIC wasn't a strategic business for IBM and so eventually they decided to sell the entire ASIC/foundry business, provided they could get manufacturing back from whoever was the buyer. Sell is a bit of a misnomer, since they actually paid GF to take it over. However, they still kept a core of semiconductor research so that they could optimize their own process, not just rely on a commercial offering available to all their competitors. As Gary put it, "that's a whole lot cheaper than owning your own fab." So that is the situation today. IBM does some semiconductor research. GF does a lot, plus all the manufacturing. There is still some level of partnership with Samsung (they had people on the fully-aligned via paper too) but when I asked Gary if they were working together on 7nm he said they were not. The GF 7nm is developed entirely in-house, although obviously building on experience from Samsung's 14nm. EUV Both Gary and Basanth talked a bit about EUV insertion. The new 7nm process (see Friday's post) is all optical. I have written quite a few posts about the issues with EUV (if you want a good overview, although it is not up-to-date, then see EUV Might Really Happen from IEDM 2015). The three big issues when I wrote the post I referenced above 2 years ago are still the main ones, namely: source power pellicle defect-free masks and mask inspection I won't go over again the bizarre light source for EUV, but the partially reflecting mirror system means that very few of the photons make it to the wafer. Getting the source power up has been a critical criterion for EUV adoption. If it is too low, the only alternative is to reduce the wafer rate and expose each die for longer. However, then EUV is not competitive with multiple patterned 193i lithography. However, ASML, the only manufacturer of EUV steppers, has been gradually increasing the power and seems on track to tick the box for this one. A pellicle is a thin transparent layer that goes over the mask. The purpose is to keep contamination from being in the optical plane and so ensure that it won't print. EUV has two additional problems compared to optical lithography. First, it has reflective optics and so the light path goes through the pellicle twice. But worse, almost everything absorbs EUV. That's why we need to run EUV in a high vacuum (air absorbs EUV) with reflective optics (so do lenses, and even regular mirrors). So almost any pellicle material absorbs too much of the EUV. It is just the same as if the source power were reduced by the same amount. The mask issue is that it is hard to impossible to build a completely defect-free mask (mirror). The masks are built up out of 40-50 layers of silicon and molybdenum. Defects in the starting material are too small to be seen by inspection. There is a big inspection problem anyway, since defects that are significant are so small, and the complete reticle is large. I have heard that the ratio is the same as looking for golf balls in the state of California. Gary explained GF's strategy. As I said earlier, 7nm will be introduced with optical 193i lithography. But they have designed the process for transparent EUV insertion. They will be able to use it for contact and via masks, and for cut masks (see photomicrograph above for some examples). Since these masks are basically a non-printing field with lots of little dots, they can get away without a pellicle, and they are much less sensitive to mask defects (they have to fall on one of those little dots to matter). There are savings in cost using EUV, since it replaces a number of optical masks with a single EUV mask, and the number of non-lithography process steps is reduced. The Frederik Philips Award Immediately after the presentation, the IEEE gave out various awards. There is an EDA connection there, even, since the IEEE President is Karen Bartleson, who was at Synopsys until recently. I interviewed Karen in only my second week at Cadence. See IEEE Elects an EDA Professional as President . Gary was one of the honorees, receiving the IEEE Frederik Philips Award “for industry influence and leadership in the development of leading-edge microelectronics technology and collaborative research.” As Gary said in his acceptance speech, he first came to IEDM 35 years earlier as a grad student. He never expected that he would find himself on the stage three decades later receiving such a prestigious award. Especially given that when he originally went to UCLA as an undergraduate, he was enrolled to study pre-law...but it turned out to be pre-engineering. But that's a story for another day. Later Watch for Breakfast Bytes later in the week with full details on the GF 7nm process that they announced at IEDM. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
↧