The title of this post says it all, but I'd better add a bit of color. Cadence was honored with an Electronic Products' Product of the Year award for the Virtuoso System Design Platform. This is the 42nd year that Electronic Products has been doing these awards—the magazine itself started in 1957—which means that they started the awards in 1975. I tried to find what products they honored that year, but failed to find anything online. But I did find some products that were introduced in 1975. The big technology one was Betamax, which was Sony's non-professional video-cassette recording system. The big non-technology one was Miller Lite, which was the first light beer. If your taste is more in the soda direction, that is the year Lilt was introduced, but you've probably never heard of it since it was only sold in the UK and Ireland. Betamax is no longer around, since it was beaten by VHS in the marketplace. However, the story is more complex since VHS was made obsolete by DVDs, which, in turn, were made obsolete by Blue-ray, which was made obsolete (or almost) by streaming. But Miller Lite and Lilt are still around 42 years later. Virtuoso System Design Platform Your first question might well be "What is the Virtuoso System Design Platform?" I'm glad you asked. For decades, there were three domains for electronic design: chip, package, board. They were largely independent. Chips were designed with some crude parasitics for the package, and a rough idea of what order the I/O pads needed to be around the outside edge of the chip. The package had to go on the board, of course, but most packages were standard designs that had been picked from a menu with a big enough cavity for the chip and enough pins. Flip-chip and complex BGA (ball grid array) packages arrived. Now, every package was a custom design. The interface to the board was usually standard, with an array of balls on a fixed grid. However, PCB routing might make some pin assignments too difficult, and at the chip level, the capacitance and inductance of the pins could no longer be assumed to be roughly the same. Since the pads on the chip where the bumps would be grown were now distributed across the die, this had an impact on place and route at the chip level, and especially on signoff timing. Depending on what type of design you were doing, Cadence had a number of product lines. But for 26 years, the heart of analog and custom digital design was Virtuoso (see Happy 25th Birthday Virtuoso for details on that). And the heart of package and PCB design was Allegro (and more recently, Sigrity for analysis). There were links between Virtuoso and Allegro in the sense that you could write out parasitic data from the PCB/package world and use it in a chip-level simulation, but that was about it. The Virtuoso System Design Platform took this integration to the next level, making it possible to open up the chip design in the context of the package and board in which it would be used. It became possible to edit the design, and simulate all or part of the design, taking into account the package and board details. If changes were made to the package, these would be incorporated automatically through the shared database, rather than requiring a file to be written out and read in explicitly. I wrote a detailed post when the product was announced, inventively titled Virtuoso System Design Platform . The above diagram shows how the various pieces fit together. The technology allows for a top-down design flow, and a bottom-up analysis flow, ensuring that everything fits together smoothly. The top part of the design, with the dark grey background, is the IC design world. The lower part, with the light grey background, is the package/PCB world. More than Moore Doing a design in a leading-edge process has become very expensive, and alternative approaches, often under the name "More than Moore", have become attractive. The heart of this is advanced packaging with more than one die in the package. This can be with an interposer (2.5D) or with die stacked using TSVs for linking them (3D), or both (putting processors alongside stacks of memory on an interposer, for example). One thing common to all these approaches is that the environment in which each chip has to function is complex, and depends on all the other parts. It is not really feasible to do this sort of design with reading and writing interfaces and hoping you got it right. Even hooking up all the signals correctly is a challenge without the databases being linked, never mind more subtle interactions like signal integrity, or power delivery network issues. As I related recently in my post Advanced Packaging Delivers More than Moore : One customer had to do a manual check of 8800 connections, and they missed two and ended up with a power-ground short; now it is completely automated and that sort of error cannot slip through. Learn More (than Moore) The best place to learn more is the product page for the Virtuoso System Design Platform. Another good place to start is my post from late last year, Advanced Packaging Delivers More than Moore , which looks at the whole trend towards doing designs with multiple die in a single package. At the recent IEDM, there was an entire afternoon focus session dedicated to 3D integration and packaging. I consider just having the session quite significant as a sign of where innovation in creating electronic systems is migrating. Normally IEDM is focused on details of very advanced research devices—just opening the program guide at random, the first paper I see is titled Sub-100nm Gate-length Scaling of Vertical InAs/InGaAs Nanowire MOSFETs on Si . My post on that session should appear in the next week or two (the 3D integration, not the InAs transistors!). Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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