Has there been enough innovation in timing signoff? Probably not, given the enormous amount of time that timing signoff and closure can take, especially at advanced nodes where there can be hundreds of multi-mode, multi-corner (MMMC) timing views. At the Design Automation Conference (DAC 2013) Monday June 3, a panel of experts will discuss how timing signoff needs to change.
The discussion will be part of a Cadence-sponsored lunch panel open to all DAC attendees. The lunch and panel will be held 11:30 am - 1:30 pm at the Austin Convention Center, Level 4, in Ballrooms E and F (see Convention Center map here). The panel is titled "Has Timing Signoff Innovation Become an Oxymoron? What Happened and How Do We Fix It?"
The panel will be moderated by Brian Fuller, who recently joined Cadence as content director/editor-in-chief. Panelists include:
- Dipesh Patel, Executive Vice President and General Manager, Physical IP at ARM
- Tom Spyrou, Design Technology Architect, Office of the CTO, Altera
- Richard Trihy, Director, GLOBALFOUNDRIES
This panel discussion will take place two weeks after the May 20 introduction of the Cadence Tempus Timing Signoff Solution. Tempus promises up to an order of magnitude faster performance than existing solutions, scales to full-flat analyses of designs with hundreds of millions of instances, and comes with an integrated optimization environment for signoff closure.One factor behind this fast performance is a clever application of parallelized computing technology to static timing analysis, as described in a blog post here.
The discussion will be interactive, so bring your most challenging questions. To register for the lunch panel, click here. For a complete listing of Cadence activities at DAC, see our DAC microsite.
Richard Goering
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