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What's Good About AMS Data Precision Options? They’re in the 16.6 Release!
Just a brief blog today to introduce that 16.6 Allegro AMS Simulator (PSpice) now provides 64-bit data precision by default. This ensures a higher precision compared to the 32-bit data. For example,...
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A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”
By leveraging Common Power Format (CPF) constructs and removing some older Unified Power Format (UPF) commands, the emerging IEEE 1801-2013 standard (UPF 2.1) will help enable "methodology convergence"...
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Virtuosity: 10 Things I Learned in April by Browsing Cadence Online Support
I'll confess: I didn't learn all of this strictly by browsing http://support.cadence.com (Cadence Online Support). I also wandered over onto http://www.cadence.com/community/blogs/ii (Industry...
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The Internet of Things – the Next Growth Driver, Enabled by High-Level...
The electronics industry has enjoyed constant growth while undergoing constant transformation. One of the most significant transformations has been the source of that growth -- from the PC revolution,...
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DAC 2013: User Perspectives on System-Level Verification
The best way to learn about an emerging technology is to hear from the people who are using it. If you're curious about system-level design and verification, you can do just that at the Cadence...
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DAC 2013: “IP Talks!” Shows What’s New in Semiconductor IP
If you're working with semiconductor IP at any phase of the design and verification process, the IP Talks! presentations at the ChipEstimate.com booth at the Design Automation Conference (DAC 2013)...
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Tempus – Parallelized Computation Provides a Breakthrough in Static Timing...
Cadence today (May 20, 2013) is announcing the Tempus Timing Signoff Solution, a new static timing analysis and closure tool that offers significant speed and capacity advantages over existing...
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What's Good About Allegro PCB Editor Quickplace Overlap? Check Out 16.6!
Just a very "quick read" on a new option for Quickplace this week.The Allegro PCB Editor Quickplace is an application used to ‘quickly’ scatter components around the perimeter of the design or to a...
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Help Shape Future Releases of APD and SiP – Provide Your Feedback on Early...
With every new release of the Cadence IC Package design software, many new features requested by designers are added. In other cases, interesting concepts that R&D engineers think up also make it...
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DAC 2013 – Cadence Customers, Partners Speak About Design Challenges and...
If you want to know how Cadence customers and partners are solving design and verification challenges, you can find out at the Cadence Theater at the Design Automation Conference (DAC 2013) in Austin,...
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SKILL for the Skilled: Part 9, Many Ways to Sum a List
In the previous postings of SKILL for the Skilled, we've looked at different ways to sum the elements of a list of numbers. In this posting, we'll look at at least one way to NOT sum a list. In my most...
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SpectreRF at 2013 IEEE/MTT-S International Microwave Symposium in Seattle,...
If you are attending the International Microwave Symposium ( IMS 2013 ) in Seattle (June 2-7, 2013) stop by the Cadence Design Systems booth, #427. We will be showing new MMSIM12.1.1 features including...
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Why are Cadence and Forte Presenting Together at DAC?
You may or may not have noticed that Cadence's DAC Theater schedule features an intriguing combination of presenters next Tuesday: Tuesday, June 04, 2013 Time Company Topic ... ... ... 11:30 AM Forte...
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DAC 2013 – Software Driven EDA for the “Age of Gods”
This year's Design Automation Conference is less than a week away, and it's time for my preview of what to see at DAC. Last year I had likened my passion for system-level design to the Energizer Bunny...
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DAC 2013: Panel to Reveal FinFET Deployment Challenges
FinFET transistors represent one of the most exciting new technology developments in recent years, and no wonder - these 3D devices promise huge power and performance advantages at 16nm and below. But...
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What's Good About PCB SI AutoSolving Models in SigXplorer? You’ll Need the...
In previous releases, when you extract a net into SigXplorer, all the structures are automatically solved in Allegro PCB SI and then passed to SigXplorer. At times, the layerstack of the extracted...
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Right Turn on Seely Avenue -- A New Blog from Brian Fuller
Years ago (and by years ago I mean so far back there’s no digital record of it), I wrote an EE Times column about a legal dispute involving Cadence. I think it had a high-and-mighty tone to it, and I...
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DAC 2013 Panel: Where’s the Innovation in Timing Signoff?
Has there been enough innovation in timing signoff? Probably not, given the enormous amount of time that timing signoff and closure can take, especially at advanced nodes where there can be hundreds of...
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Mixed-Signal -- Successful Tech-on-Tours, Huge Focus at DAC 2013
We just completed some hugely successful Mixed-Signal Tech-on-Tours in North America. I am back in San Jose after this whirlwind trip that covered 9 cities in 4 weeks. Even though being on the road...
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Customer Support Recommended - Flex PCB Design Features in Allegro PCB Editor
Flexible PCBs are used widely in everyday technology and electronics in addition to high-end, complex completed components. Two of the most prominent examples of flexible circuit usage are in hard disk...
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