We’re thrilled to have announced our prototype 7nm DDR5 IP silicon based on a preliminary version of the DDR5 standard at this week's TSMC Technology Symposium. This has been a huge amount of work from the DDR teams at Cadence and sets a landmark for the adoption of a new memory standard in the industry. This has been quite an experience for us, starting in 2017 when we developed the prototype DDR5 PHY and DDR5 Controller IP, basing it on preliminary ballots and discussion on the DDR5 standard which even today has not yet been released. Fortunately, we have a lot of silicon ‘firsts’ and one of the hallmarks of our IP is its adaptability, we were able to put enough flexibility into the design to ensure first-time silicon success. We also had the benefit of Cadence’s DDR5 VIP (Verification IP) throughout the design process, using an independent team inside of Cadence who were also looking at the DDR5 standard development at JEDEC and with our industry partners and encoding that into the memory model that we used to verify the DDR5 IP. Once we taped out our testchip containing the prototype DDR5 Controller and PHY IP, there was the customary manufacturing period, of course. We used that time for continuous improvement of the IP and its deliverables, but I can tell you it’s very much like parents anticipating the arrival of a new baby. When the testchip silicon came back it was “go time”. The IP supports both DDR4 and the preliminary DDR5 ballots, so we used DDR4 mode initially to test the silicon. Since we already have fully characterized DDR4 PHY and Controller IP testchips in TSMC 7nm, 16nm and 12nm nodes and a lot of experience working with the TSMC 7nm process, we had high confidence that DDR4 mode would work in this testchip and we got full speed DDR4-3200 working very quickly. In parallel we were finalizing all the details of the prototype DDR5 parts with our friends at Micron, we received the actual prototype DDR5 DRAM parts from Micron, and when everything was set we sent the DDR5 printed circuit boards (PCBs) off for manufacturing and populating with the Cadence testchip and the Micron DDR5 DRAM prototypes. When the DDR5 PCBs came back, we got the first transactions running in preliminary DDR5 mode using the signaling voltage, impedance and protocol from the preliminary DDR5 ballots. Thanks to some very hard work from our lab team, we were able to quickly ramp up the speed to the full rated data rate of the prototype IP, DDR5-4400. And here we are today! Be sure to check out the demo video and other informative material on the DDR IP page .![]()
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