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DDR-PHY-DFI-OMG-BBQ
Today Cadence's clipping service found a quote by Cadence in a press release by DFI Group, and when I first read about it, it was as if my brain stopped understanding what was clearly English....
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The San Jose Tech Museum
Last summer, I did a series of posts about technology museums. If you missed them, here are the links: The Intel Museum German Computer Museums British Computer Museums The Computer History Museum Four...
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Leading the Charge: Cadence Announces New Verification IP for UFS 3.0,...
On April 17, 2018, Cadence announced three new VIPs, two of which are industry-firsts! Cadence revealed the first available VIP for CoaXPress for high-speed imaging and the first available VIP for...
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How We Developed and Tested a Prototype DDR5 Interface in Silicon Based on a...
We’re thrilled to have announced our prototype 7nm DDR5 IP silicon based on a preliminary version of the DDR5 standard at this week's TSMC Technology Symposium. This has been a huge amount of work from...
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What's For Breakfast? Video Preview May 7th to 11th 2018
https://youtu.be/OJRKUHltc1c Coming from Teske's Germania (camera Sean) Monday: TSMC Fab Plans and More Tuesday: embargoed announcement Wednesday: Digital Marketing in EDA Thursday: CDNLive EMEA 2018...
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TSMC Technology Symposium 2018
This week it was the TSMC Technology Symposium in Silicon Valley. Dave Keller, president of TSMC North America was the MC for the day. Dave kicked off by giving a few statistics about TSMC's business...
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How We Developed and Tested a Prototype DDR5 Interface in Silicon Based on a...
We’re thrilled to have announced our prototype 7nm DDR5 IP silicon based on a preliminary version of the DDR5 standard at this week's TSMC Technology Symposium. This has been a huge amount of work from...
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TSMC's Fab Plans, and More
The TSMC Technology Symposium took place recently. I grouped all the process and packaging roadmap into my previous post TSMC Technology Symposium 2018 . Today I'll look at the rest of what was...
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What's For Breakfast? Video Preview May 14th to 18th 2018
https://youtu.be/T4Pu_l6upso Coming from Englischergarten Munich (camera Andy Le) Monday: Agile Development of Custom Hardware Tuesday: CDNLive EMEA Session Wednesday: TSMC: Mobile, HPC, IoT,...
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Legato: Smooth Reliability for Automobiles
In his keynote at ICCAD in 2014, Bosch's VP engineering Peter van Staa said that EDA would "probably not" solve the problems of automotive, since they are totally focused on the leading-edge nodes....
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Whiteboard Wednesday - Introducing the DFI 5.0 Interface Standard
In this week’s Whiteboard Wednesday, John MacLaren, chairman of the DDR PHY Interface Group, describes the new DFI 5.0 specification and the enhancements it provides to the Controller/PHY Interface of...
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Digital Marketing in EDA...with No Hands on the Wheel
Years (decades) ago, Robert Townsend, the CEO of Avis, faced a problem. Hertz was several times as big as Avis. Avis was losing money. He asked the Bill Bernbach, the head of his advertising agency...
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Why Silicon Photonics Are a Wave of the Future (or Are They a Particle?)
The movement of information using light is nothing new. Fiber optic communications networks are commonplace in data and telecommunications systems. Advances in IC technology and fabrication are now...
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Make Reliable Designs That Won’t Fail In The Real World!
Recalls are never fun and are costly. Reliable designs are crucial where they can: • Potentially save the product (or the company) from failing • Preserve the reputation of the company and products •...
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CDNLive EMEA, Driving to the Future
This week it has been the 13th European CDNLive, held in Unertschleißheim in the suburbs of Munich. The event starts on Monday afternoon with some technical tracks. The big day is Tuesday, starting...
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Power-Aware SI DDR4 Simulation: You Have a Choice!
Simultaneous switching noise (SSN) caused by simultaneous switching outputs (SSO) has been a hot topic for decades in signal integrity (SI) circles (see figure to the right). Some claim only a SPICE...
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Compromising a Fortune 500 Company...Without Hacking a Thing
Rachel Tobac and Joe Gray opened their talk at RSA by highlighting how important social engineering has become. For example, Ubiquity Networks lost $39M in 30 minutes through social engineering....
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Agile Development of Custom Hardware
It was back in 2016 that I first heard about RISC-V, and the Raven implementation, and the Chisel hardware design language that Berkeley had developed. See my post A Raven Has Landed—RISC-V and Chisel...
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Status of Verification Education in Academia
Since I’ve started working for Cadence Academic Network three years ago, when talking to big Cadence customers sooner or later they mention the verification topic. The need for verification is...
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How Do You Change What Happened in the Past?
In researching and thinking about silicon photonics last week, I found myself going down the rabbit hole of quantum physics. Like ya do. Since I didn’t take any physics classes in college, most of what...
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