At the imec technology forum (ITF) held the day before SEMICON West opened, two of the presentations were about future technologies, one focused on the FEOL, front-end-of-line, meaning the transistors. The other was focused on BEOL, back-end-of-line, meaning interconnect. These days there is also an MEOL, middle-end-of-line, which is the local interconnect that can be used within cells and memories, but has very restrictive design rules and limited things that it can be used for. Together, these presentations give an overview of what a process beyond 5nm is likely to look like. The two presentations were: Dan Micuta on Nanosheets, CFETS: A Perspective on Logic Scaling and Beyond Szolt Tokei on New Conductors: Reality or Not? Dan Micuta I hope it is no surprise to anyone reading this that simply scaling the process and keeping everything else unchanged has run out of steam. The first critical dimension for a process is the contacted-poly-pitch, or CPP. This is basically the spacing of the transistors. The other is the Mx pitch, the tightest metal pitch, typically metal2. The big problem is the CPP, which has stopped scaling. We do have some tricks left, in particular, contact-over-active-gate (COAG) which is just what it sounds like. But there still needs to be room for the fin and the work function material between. The metal pitch is continuing to scale for now, although the challenges there are less with lithography and more with the rapidly increasing resistance. Current metal technology involves copper as the conductor. But copper requires a thick barrier material lining the trenches of long interconnects and also lining the contact/via holes. This barrier is of a constant thickness independent of the width of the interconnect, so as we shrink, there is less and less room for the actual copper. Another key issue, is that at the bottom of the contact/via hole, the liner goes across the bottom of the hole (think of a can with no top as the liner) meaning that the current actually has to flow through the liner. As you can see in the above diagram, the solution to get scaling to keep on the 50% per node cadence, has been DTCO, design technology co-optimization. If you want more detail on this, see my post after my visit to imec this May Imec Roadmap . Basically, this is taking tracks out of standard cell libraries and adding scaling boosters to the process to make this possible. Also, as part of this process, reducing the number of fins in a transistor, known as fin depopulation (which sounds like a hipster word for over-fishing). Once the fin depopulation goes down to one fin (and it goes without saying that it can't go lower) then the limited drive and higher leakage start to cause a problem (I was going to say "problematic" but that is such a SJW word these days that writing it is...problematic). It doesn't change the cell architecture much, but the requirement is to switch to some form of gate-all-around. The direction everyone seems to be going is to nanosheets, where the channel material is flattened into an oval, to increase the drive current. It is worth emphasizing that each scaling booster is a one process node boost. For example, adding contact-over-active-gate give you a boost, but then you have to keep doing it for all future processes without any incremental gain. Of course, taking a track out of the standard cell height is the same. If you reduce the tracks from 5 to 4, then you have to stick with a maximum of 4 from then on. It's not like shrinking the metal pitch itself, where, at least in principle, you can shrink it some more next time. One especially important scaling booster is buried power rail. Of course, this is also a one-time gain, but it is a big one. In a modern SoC, the power (which is in the interconnect layers, of course) takes up an increasing amount of the available space. Although it typically has dedicated or near-dedicated layers, they are high up in the metal stack, but the power has to get down to the transistors through all the intermediate layer. It is a bit like a drilled hole in a PCB, which has to be accommodated on all the layers, not just the ones that are going to be connected through the hole. Buried power rail moves the power distribution network into the substrate. The power still has to get to the transistors, of course, but in effect the power is now in the FEOL and impacts only the very lowest levels of metal. This allows the number of tracks in the cell to be further reduced (since previously 1 (or more often 1.5) tracks were needed for the power. If you are thnking that once you bury the power rail, why would you not power it from the backside and build the PDN on the backside of the wafer, and connect with TSVs to the buried rails? Yes, that is also on the roadmap, but first there is another challenge. Buried power rail means that the spacing between the P and N transistors in a cell is getting closer than we can deal with, <30nm. For all sorts of reasons, we can't really have the track spacing in the middle of the cells be larger than elsewhere, unless it is a whole track which defeats the purpose of removing a track. The most attractive solution to that problem is to put the two transistors on top of each other, as in the above pictures, with the NFET folding over the PFET. This is known as Complementary-FET or CFET. We can even, as a first step, go back to a two-fin device. Another advantage is that the CFET cells are place & route friendly, making pickup of signals straightforward. Of course the biggest advantage of all is that they reduce the area of the transistors by about 50% since they only take up the space of one transistor since the other is hidden in the attic like Mr. Rocheter's wife. In the SRAM, which these days is typically more than half most SoCs, the CFET is also friendly, allowing the pass transistors to hide in the attic too. It is easy to say "just" stack the transistors on top of each other, but is it actually practical (and economically reasonable) to have a process that does this. Imec have done this successfully, using the process above (obviously there are lots more process steps when you dig into the details). Bottom line on everything said so far: using GAA can reach the requirements for 2nm transistors, and CFET give a big increase in area scaling. So there is a route to 2nm that is workable. Szolt Tokei Enough FEOL stuff, how about some BEOL. The above picture shows all the materials we might use for interconnect. The two axis are the melting temperature (required for annealing in most cases) and the current carrying capacity. We want a low temperature and a high current carrying capacity. Since we currently use copper, we are really only interested in materials that end up in the green rectangle that are better than copper. We are not going to go back to aluminum, for example. It has a very low melting point, which is why we used to use it, but it doesn't carry so much current, which is why we abandoned it for copper. Pop quiz: can you name all the elements in the table above? Hint: Ru is not Rubidium. Ranked by merit we end up with Rhodium, Gold, Iridium, Ruthenium, Cobalt, Tungsten, Molybdenum, Nickel, and default choice Copper. However, some of the elements are pretty pricey, especially when compared to copper. For example, Rhodium is getting on for 1000 times more expensive than copper. There is another weird interconnect effect associated with grain size. For short lengths, some materials are better than copper, whereas for longer lengths, copper wins. Ruthenium is even better than Cobalt below about 12nm, and is even better than it seems for contacts since it is almost barrierless. In the short term, for logic, Cobalt and Ruthenium are attractive, and in the longer term it looks attractive to investigate some compounds, as opposed to pure metals. Memory, which has different cost, performance, and current limits probably has a slightly different roadmap in terms of attractiveness. I talked above about buried power rail without saying what material it would be made out of. In general, one challenge with semiconductor manufacture is that everything in the FEOL has to be able to survive going in the furnaces, whereas the metals involved in the BEOL have much lower melting points and so can't take those temperatures. Copper and Aluminum, the two main interconnect metals of the last 50 years, both have low melting poinys are are FEOL incompatible. Actually, Copper is incompatible for contamination reasons. Once a wafer gets copper on it, it is never again allowed near the FEOL and if it is in a single wafer plastic case, it will have an orange piece of tape on it to show it has copper. Here is a picture of me, holding a 450mm wafer (they are big!) with its orange copper indicator tape. As you can see from the tabble above, copper is red for everything except its low resistance. Tungsten and Ruthenium seem to be the materials of choice. Finally, as you can see from the above diagram, once you go beyond pure metals to compounds, then there are a lot of choices. A lot of the periodic table lights up with compounds of a metal (in red) and a non-metal (blue). There is a lot of work to be done to test these out, but something unusual might turn up as being ideal. Who had ever heard of Hafnium before it showed up in HiK metal gate transistors? The conclusion of Szolt's presentation is that we need better and more cost-effective materials for interconnect for both memory and logic, alternatives are emerging, and the R&D pipeline is filled with materials beyond pure metals. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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