One of the sessions at HOT CHIPS is on new technologies, and one of those presentations was by Bill Gervasi of Nantero on Architecture for Carbon Nanotube Based Memory (NRAM) . The technology sounds too good to be true, as someone in the audience said during the time for questions afterwards. It is faster than DRAM. It is cheaper than DRAM. It has greater capacity than DRAM. It is persistent (which, apart from the persistence aspect, also means it doesn't need to spend about 15% of its time on refresh, and other things). Unlike flash, it has no wear out. Persistence seems to be infinite, or measured in hundreds of years. There doesn't seem to be any temperature sensitivity, at least below 300°C. And if space is your thing, it appears to be immune to alpha particles. I happened to talk to Bill during the social hour after the first tutorial day, before I'd seen the presentation. It sounded intriguing, and even more intriguing after seeing the presentation. Who is Nantero? They are an IP company, so they don't build their own products, they license them. They have been around for quite some time developing the technology. The one licensee he could talk about was Fujitsu, who had announced a few weeks before that they would take the technology to mass market starting next year. What is CNT Nonvolatile Memory? The memory works using the Van der Waals effect which keeps nanotubes that are apart apart, and keeps nanotubes that are together together. Van der Waals forces are attractive or repulsive depending on distance. It takes a pulse of energy to switch them in both directions, which is where the non-volatility comes from. The energy requirement is 5fJ/bit (compared to 5-7fJ/bit for DRAM, so compatible) in the form an electrostatic pulse, voltage down the word line, with activation through an associated bit line. Some of Nantero's secrets are involved in how they prevent sneak to adjacent bit lines. One weird characteristic of the memory is that writes are faster than reads. The above diagram shows the CNTs near the bottom electrode pushing up towards the top and opening up a gap. The resistance between the two electrodes changes by 10X, so detecting the difference between 0 and 1 is not hard to detect and there is no need to calibrate across the wafer. There are between hundreds and thousands of CNTs per bit cell. The top tubes don't move and don't participate in the bit storage—they are there to prevent the metal sputtered on to make the top electrode from permeating all the way and shorting out the cells. The cells either stay apart or stay together, driven by the Van der Waals forces. The manufacturing process is simple, at least the way Bill described it: Build the die normally. Spin coat carbon nanotube slurry, bake it, sputter metal, etch, seal, done. Having said that, in the questions, Bill said that: Part of our secret sauce is the formula by which we create the CNT slurry. We build the machines for that, and licensees clone them. Each CNT cell has a certain diameter, certain vertical height, and the CNT diameter and length have to be chosen for that. The CNTs need to be the right diameter and length for the process technology. If they are too long, then they won't move when switched, and if they are too short, they can end up standing vertically and not switching either. Bill didn't say anything about it, but I know one problem with making CNTs is that some of them turn out to be metallic (conductors) but in this stochastic configuration where lots of tubes are used to store a bit then I assume this doesn't matter (it matters a lot if you try and build transistors using CNTs for the channel, since you can't turn off a metallic "CNT"). The NRAM is built on top of the top layer of the die, and so can be added on top of any technology. It doesn't even have to be silicon (or even logic). Scaling NRAM Initially, Nantero and their licensees are targetting drop in DDR4 replacement, moving later to DDR5 replacement as that transition takes place in the DRAM market. The technology can be further scaled though: Add more layers of CNTs Standard die stacking using TSVs (like hybrid memory cube). Process scaling is a function of the number of CNTs per bit and is well understood all the way down to 5nm and beyond. Today there is one bit per cell, but multi-level cells can be built as a function of the pulse. Persistence There is increasing interest in persistent memory and making the software aware of it. Some of this is driven by 3D X-point (which Intel calls Optane). Some is driven by NVDIMMs, which are actually complex DIMMs that have the DRAM, some NAND to hold the backup, and a battery (or big capacitor) to keep it all working over a power fail since it might take several minutes to copy the DRAM to flash or back. With NRAM, there is no need for either the power source, nor the backup flash. 3DXpoint (aka Octane) is called "storage class memory." Bill likes to call NRAM "memory class storage." Architecture Above is the architecture of a DDR4 NRAM chip. The dark blue parts are standard DDR functions. The orange are the NRAM components. The pale green are added value blocks that may or may not be present. Summary If this technology is really as good as it appears, I don't understand while all the DRAM manufacturers (or people that want to compete with them) haven't licensed this technology and built gigscale fabs to manufacture it. Advances in DRAM are getting really difficult and so going really slowly. In fact we are scaling DRAM bit volume mostly by building more and more fabs, not by getting more and more bits per wafer. That is unsustainable. Lots of technologies, various flavors of MRAM, RRAM, spin technologies, and so on, have looked like the answer to be "what comes after DRAM". So the big question for me is whether this is, as it looks on the slides, a technology that can take over after DRAM, or if it has some fatal flaw nobody in the audience at HOT CHIPS seemed to spot. But given that, here is the summary: Electrostatic effects set & reset each bit Resistance delta of 10X allows reliable sensing Dielectric-free cell shows no wear-out DDR4 NRAM includes a DRAM-compatible front end Defines a new category “Memory Class Storage” NRAM per die capacity scales far beyond DRAM Fully deterministic timing better than a DRAM On-the-fly ECC incorporated for server class reliability Module level NRAM products are plug and play compatible Industry is ready for persistent main memory Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
↧