Chris Rowen has been at the leading edge of semiconductor technology for many years. In 1997 he launched Tensilica, a company that revolutionized system-on-chip (SoC) design with its XTensa configurable dataplane processing IP. Following the Cadence acquisition of Tensilica in 2013, he became a Cadence fellow, and he's still actively involved in the development and deployment of dataplane processing IP.

In this interview, Rowen talks about his background, the founding of Tensilica, the importance of dataplane processing IP, the advantages of the Cadence acquisition, and current trends impacting the IP and EDA industries.

Q: Chris, when and why did you start Tensilica?

A: Back in 1997 I was working in the EDA/IP business, and I came to realize that the key IP for the future of SoCs was going to be processors. This didn't fit into other people's conceptions of the EDA and IP business, so I realized I needed to start my own company. I set up shop in my living room and started pursuing the idea of processors for SoCs.

This turned out to be a fruitful line of inquiry, because processors historically were developed as standalone chips. Those chips were intended to be very general purpose. But on an SoC, everything else on the chip was application-specific. So we asked the question, why not make the processor more application specific? And what would the benefit be?

We saw that if you make the processor more application-aware, you could run a lot faster and run at lower energy. But there was a technical hurdle, because people expect processors to come with a large software ecosystem with compilers, debuggers, simulators, RTOS, and applications. Our premise was that if we could automate the generation of correct [processor] hardware and complete software, there would be a very large market in application-specific roles. And we made that breakthrough in processor automation.

Q: What was your background before Tensilica?

A: I worked in semiconductor testing and process technology with SRAMs at Intel. I then went to graduate school at Stanford and worked with John Hennessy [now Stanford president] who was then a young assistant professor working with compilers and a new processor design that later became known as RISC. I was one of the Stanford guys involved in the MIPS RISC project, and we started the company MIPS and developed the first MIPS architecture in 1984.

I had a lot of different roles at MIPS and its successor, Silicon Graphics. Then I went to Synopsys for a brief time to run its IP business. Then I started Tensilica.

Q: Tensilica introduced the notion of dataplane processing IP. Why was that a significant development?

A: There were many isolated cases of programmable processing for heavy data applications, but we really unified and systemized the thinking around them. DSPs, which are a subcategory of dataplane processors, have played important roles, but there are many flavors of processors besides DSPs - such as network processors, protocol processors, and security processors.

We started with an underlying technology that allows us to generate the instruction set, memory hierarchy, interfaces and software tools that are appropriate to an application, with great flexibility about the details of that instruction set. We provided a single kit that allowed the SoC design team to do many different tasks with the same toolset.

Q: Who uses Tensilica DPUs [dataplane processing units] today, for what types of applications?

A: We have over 200 licensees, mainly semiconductor companies from the biggest to the smallest. They are building a wide variety of different products, from SoCs that go into cell phones to televisions, wireless access equipment, and base stations. DPUs are used in almost any kind of electronics that draws power and has digital logic inside.

Q: Configurability is an important aspect of the Tensilica DPU technology. What is the importance of configurability?

A: From a customer standpoint, the first form of configurability they care about is programmability. You could say a general-purpose CPU is the most configurable of all, because you can run any software on it, perhaps all of it badly from an energy standpoint. In our view configurability is the way you take programmability and make it efficient. It allows you to decide what parts of the problem are most likely to change, and therefore should remain entirely in software, and what parts are less likely to change and can be optimized with  hardware.

Configurability and its first cousin, extensibility, go hand in hand. Configurability allows the customer to choose from a broad spectrum of previously imagined or defined choices. Extensibility is the idea that each architecture team can determine for themselves what instruction set and interface they need. Rather than working from scratch, they can express their proprietary configuration at a high level. In our case they work with the Tensilica Instruction Extension [TIE] language.

Q: What are the advantages of the Cadence acquisition for Cadence, Tensilica, and our mutual customers?

A: The acquisition gives Cadence an additional avenue to engage with customers. Tensilica is routinely involved in discussions with the customers' product architects and planners about what is going into an SoC. For Cadence, the acquisition provides a new way to engage earlier and in a more strategic fashion in some of the most important projects of its customers.

For Tensilica, Cadence brings the corporate strength of a big public company with a large sales and support organization. We can go into any design team without hearing the question, will you be around 10 years from now? People don't think about dating their processor, they think about marrying their processor. It's a very long-term relationship because the customer team is going to write a lot of software and gain a lot of knowledge about the processor and its tools. It's just easier if they're looking at a big public company as their long-term partner.

From a customer standpoint, the acquisition provides a greater ability for us to invest for the long term. Customers will have a rich roadmap of new capabilities and a guarantee of longevity.

Q: What do you see as the future of dataplane processing IP?

A: There are two key directions. One theme is that many of the functions people are doing, in imaging, audio and baseband, are so complex that what was once hardwired logic needs to become more programmable. So dataplane processors are becoming an alternative to other kinds of dataplane logic.

The other major theme is driven by the quest for cost efficiency and energy efficiency in computation. Very often, it makes sense to offload a category of computation from the main CPU into some complementary processors and free up expensive computational resources on the main CPU.

Q: Taking a broader view, what general trends do you see in the IP industry today?

A: Clearly systems companies are moving up - they're thinking about the cloud, distributed applications, services, and networks, not about individual devices. Chip companies are becoming much more sophisticated about building systems and are creating much more software. I think this calls for [IP] subsystems, and there will be a lot more software coming in to serve those subsystems. You can't just plug together several pieces of IP to make a subsystem, because you're talking about something that has a lot more software content than when people talked about cores or IP blocks.

Q: And now that you're at Cadence, what trends do you see in EDA?

A:  I see three big trends. One is that the complexity of chips has become so daunting that new methodologies, such as large-scale emulation and structured methods of verification, are becoming more important. A second trend is that SoCs are integrating many different kinds of components, not just RTL but also analog/mixed-signal blocks. All must come together in a modeling and verification infrastructure that can ensure the chip is correct.

The third major force is the growth in software complexity. However fast the growth in hardware complexity, the growth of software complexity is even faster. You can't talk about just simulating the hardware, you have to simulate the application running on the hardware. Hardware by itself cannot be deemed correct. I think software-driven SoC design will be a big theme.

Richard Goering

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