Clik here to view.
DAC 2013 at 50: EDA Memories and Moments
AUSTIN, Texas--The just-concluded 50th Design Automation Conference offered the usual robust exhibits and technical sessions, but this year for the big anniversary it also served as part museum of...
View ArticleClik here to view.
DAC 2013: Qualcomm, TI Keynoters Present Mobile SoC Design Challenges and...
Keynote speeches at electronic design conferences tend to focus on high-level industry issues. The "Designer Keynote," part of the Designer Track at the recent Design Automation Conference (DAC 2013),...
View ArticleClik here to view.
What's Good About RF PCB and Agilent ADS Via Exchange? 16.6 Has Many New...
The 16.6 Allegro PCB Editor and the Agilent Advanced Design System (ADS) interface have several new enhancements with respect to padstacks and vias.I will cover the Allegro generic via padstack that...
View ArticleClik here to view.
DAC 2013 Panel – Can Better Organization Solve the Verification Crisis?
Automated tools and standardized methodologies have made functional verification easier, but verification is still arguably the biggest bottleneck in getting chips out the door. The good news,...
View ArticleClik here to view.
Communications, Collaboration and the Need for More Women in Engineering
AUSTIN, Texas-Kathryn Kranen was in a jam. The CEO of Jasper Design had prepared a presentation for the last day of Design Automation Conference, Thursday. Problem was, the presentation was effectively...
View ArticleClik here to view.
We Need to Move "Past EDA": Tensilica Founder Rowen
AUSTIN, Texas—The EDA industry needs to move beyond EDA. Sound counterintuitive? Not so much when the words come from the lips of Chris Rowen, the founder and CTO of Tensilica, and a guy I consider one...
View ArticleClik here to view.
Software as a Service (SaaS) Lowers the Bar for IC Design
One reason you don't see a lot of semiconductor startups is that it's very costly to build a hardware and software infrastructure for IC design. But there's an alternative to buying a bunch of servers,...
View ArticleClik here to view.
Archived Webinar: How Cadence and TSMC are Easing Layout-Dependent Effects
At 28nm and below, the performance of a device can vary greatly depending on what it is placed near in the layout. For this reason, layout-dependent effect (LDE) is one of the most challenging aspects...
View ArticleClik here to view.
25 Years of Innovation: Then, Now, and the Road Ahead
In 1988, Ronald Reagan was wrapping up his second presidential term in Washington. Perestroika came to the Soviet Union. NASA reported accelerated breakdown of the ozone layer by chlorofluorocarbons....
View ArticleClik here to view.
TSMC Native SKILL PDKs Tune Virtuoso for 16nm FinFET Design
Custom/analog designers working at FinFET process nodes are going to need all the help they can get. As announced by Cadence today (July 8, 2013), TSMC will help out by providing native SKILL-based...
View ArticleClik here to view.
How-To AppNotes on Cadence Palladium-XP Help Users Get the Basics Right
In simulation acceleration, there are multiple reasons for using gate-level netlists in place of RTL code. One reason is the reuse of mature code or third party IP that is supplied in netlist format...
View ArticleClik here to view.
What's Good About FSP’s Schematic Generation? 16.6 Has Many New Enhancements!
The 16.6 release of Allegro FPGA System Planner (FSP) has MANY new enhancements in the area of schematic generation.Some of the highlights:Rules file can be added via the Component Browser as Real...
View ArticleClik here to view.
M-PCIe—The New Big Thing from MIPI Alliance and PCI-SIG
If you’re reading this, you must have heard about the M-PCIe specification that has just been announced by two very important standardization bodies in the semiconductor industry—MIPI Alliance and...
View ArticleClik here to view.
Cadence Verification IP AppNotes Demonstrate the Use of Trace Files in...
Cadence Verification IP (VIP) provides solutions for verifying compliance and compatibility of protocols. All VIPs include highly configurable and flexible simulation models of all protocol layers,...
View ArticleClik here to view.
Bending a Few IC Package Design Rules – With Confidence
Somewhere out there is an IC package designer who has been given design guidelines and cannot possibly meet the maximum layer constraints. You probably know this guy or gal (let's call her a gal). What...
View ArticleClik here to view.
Virtuoso Electrically Aware Design (EAD) – A New Approach to Custom/Analog...
The term "paradigm shift" is overused, but I think it just might apply to the Virtuoso Layout Suite for Electrically Aware Design (EAD) product announced by Cadence today (July 10, 2013). Behind this...
View ArticleClik here to view.
Customer Support Recommended - Working with NetGroups in Allegro Design Entry...
Allegro Design Entry CIS provides a new feature called NetGroup, which offers an easy-to-use and more flexible method of connecting schematic symbols in complex designs using the concept of bundling...
View ArticleClik here to view.
The Future's in Our Hands; Let's Not Blow It
SAN FRANCISCO--Any time I sit down to listen to an industry forecast, I end up with the same feeling as I get when I walk out of a hyped Hollywood movie: Is that all there is? The outlook is inevitably...
View ArticleClik here to view.
Q&A: Tensilica Founder Chris Rowen – Perspectives from an IP/SoC Pioneer
Chris Rowen has been at the leading edge of semiconductor technology for many years. In 1997 he launched Tensilica, a company that revolutionized system-on-chip (SoC) design with its XTensa...
View ArticleClik here to view.
Virtuosity: 20(!) Things I Learned in June by Browsing Cadence Online Support
Wow! There was an amazing amount of new content added last month. A lot of new videos and some Really Useful articles. Enjoy.Rapid Adoption Kits1. CPF-AMS Low-Power Mixed-Signal SimulationCPF-AMS is...
View Article