A lot of aspects of EDA and semiconductor are fairly easy to predict: you read off the process roadmap for the big guys and work out the implications for tools, IP, and methodology. Of course, it is harder back away from the leading edge since that is not driven by technology: it is a lot less clear what are the business opportunities for, say, 90nm and whether there are aspects of leading-edge design tools that should be back-ported to 90nm. After all, despite the leading edge getting all the glory, a lot of designs are done at 28nm, 90nm, and even "older" technologies. But the leading edge is driven by process technology. To be fair, process technology is driven by equipment technology, especially in the lithography area, and especially the implications of the introduction of EUV into volume manufacturing. To find out what is going on at the top of the funnel of process technology, I think the two top resources are following what imec is doing (since they look at everything and work with everyone), and attending IEDM, the International Electron Devices Meeting. The weird name is because it has been going on for 64 years back, and when it started an "electron device" was a vacuum tube (valve in UK), transistors were relegated to a little section on the last afternoon, and integrated circuits had still to be invented. IEDM 2018 IEDM is December 1st to 5th at the Hilton Union Square in San Francisco (as it will be for the foreseeable future since they no longer alternate with Washington DC). The day-by-day format is the same as usual: Saturday 1st: Tutorials Sunday 2nd: Short Courses Monday 3rd: Plenary Session in the morning Monday afternoon until Wednesday 5th: about ten parallel tracks, including some special focus sessions. IEDM Late News: 3nm and DRAM Scaling Slotted in at the last moment are a couple of "Late News Papers." These are traditionally from industry leaders revealing the first details about their next-generation processes. There are two this year, one from Samsung on their 3nm GAA (gate-all-around) logic process, and one from imec on continued scaling for DRAM. These are probably the biggest discontinuities in semiconductor leading edge, since the third key technology, flash, has already gone through its big transition to 3D. Paper 28.7: First Steps Toward 3nm CMOS Technology. Samsung researchers will describe their 3nm CMOS technology featuring gate-all-around (GAA) transistors with channels made from horizontal layers of nanosheets that are completely surrounded by gate structures. Samsung calls this a Multi-Bridge-Channel (MBC) architecture, and says it is highly manufacturable as it makes use of ~90% of the company’s existing FinFET fabrication technology, requiring only a few revised photomasks. They built a fully functioning high-density SRAM macro with it. They say the process demonstrates excellent gate controllability (65 mV/dec subthreshold swing), 31% higher on-current than the company’s FinFET technology, and offers design flexibility because the nanosheet channel widths can be varied by means of direct patterning. One image from the paper shows the MBC FET to the right. Paper 2.7: Scaling DRAM Technology To 16nm And Beyond, DRAM memory technology is used in virtually all electronic systems because of its speed and density. DRAM memory comprises arrays of capacitor-transistor pairs which store data as electrical charge in the capacitor. It’s difficult to scale DRAM to the 16nm generation and beyond because of space limitations which make it hard to pack enough capacitance within the pitch. imec researchers used an atomic layer deposition (ALD) process to pattern and build a novel 11nm pillar-shaped capacitor using new dielectric materials (SrTiO 3 , or STO). By tailoring the material properties of the capacitor and the SrRuO 3 (SRO) epitaxial template on which it was grown, the researchers achieved a very high dielectric constant (k~118) and low electrical leakage (10 -7 A/cm 2 at ±1V). This means that pillar-shaped capacitors can be used instead of existing cup-shaped capacitors, without paying too great a penalty in terms of reduced data-storage capability. These results make the STO capacitors suitable for continued scaling for 16nm and smaller DRAMs. IEDM Tutorials On Saturday, there are 6 tutorials, given in three parallel sessions in morning and afternoon: Emerging Device Technologies for Neuromorphic Computing, Damien Querlioz, CNRS Reliability Challenges in Advanced Technologies, Ryan Lu, TSMC Quantum Computing Primer, Mark B. Ritter, IBM Design-technology Co-optimization at RF and mmWave, Bertand Parvais, Imec STT-MRAM Design and Device Requirement, Shinichiro Shiratake, Toshiba Memory Power Transistors in Integrated BCD Technologies, Hal Edwards, Texas Instruments IEDM Short Courses On Sunday there are two short courses given in parallel (so you can only attend one). Traditionally, one is logic-focused and one is memory-focused, and this year sticks to tradition. Despite being called "short", these courses actually last all day. This year they are: Short Course 1: Scaling Survival Guide in the More than Moore Era Extreme-UV lithography – Principles, Present Status and Outlook, Tony Yen, ASML MOSFET Scaling Knobs (GAA, NCFET…) and Future Alternatives, Witek Maszara, GlobalFoundries Overcoming Variation Challenges, Sivakumar Mudanai, Intel 3D Integration for Density and Functionality, Julien Ryckaert, imec Advanced Packaging: the Next Frontier for Moore’s “Law”, Subramanian Iyer, UCLA Embedded Memory: Present Status, and Emerging Architecture and Technology for Future Applications, Eric Wang, TSMC Short Course 2: It ’ s All About Memory, Not Logic!!! DRAM : Its Challenging History and Future, Dong Soo Woo, Samsung 3D Flash Memories: Overview of Cell Structures, Operations and Scaling Challenges, Makoto Fujiwara, Toshiba Emerging Memories including Cross-Point, Opportunities and Challenges, Kiran Pangal, Intel Memory Reliability, Qualification and their Relation to System Level Reliability Strategies, Todd Marquart, Micron Future of the Packaging Technologies for HBM, Nick (Namseog) Kim, SK Hynix Processing in Memory (PIM): Performance and Thermal Challenges and Opportunities, Mircea Stan, University of Virginia IEDM Plenary Session Monday opens with the plenary session. This starts out with a welcome to IEDM and various awards, followed by three keynotes. This year the keynotes are: 4th Industrial Revolution and Foundry: Challenges and Opportunities , Eun Seung Jung, President of Foundry Business, Samsung Electronics Venturing Electronics into Unknown Grounds , Professor Gerhard P. Fettweiss, TU Dresden Vodafone Chair Mobile Communications System Future Computing for AI , Dr. Jeff Welser, Vice President and Lab Director, IBM Research Almaden IEDM Focus Sessions During the remaining two and a half days there are specialist sessions on areas of device physics that you really have to be a researcher in the area to completely understand. Sprinkled through are focus sessions of a more general nature. I'll just give you the topics: Quantum Computing Devices Future Technologies Towards Wireless Communication: 5G and Beyond Challenges for Wide Bandgap Device Adoption in Power Electronics Interconnects to Enable Continued Technology Scaling But there is more in a zillion other sessions, including Neural Networks, Memory Technology, Advanced CMOS, Photonics, and more. Learn More Full details, including links for registration, are on the IEDM website . Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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