Coming up in December, in the same week as IEDM, is the RISC-V Summit at the Santa Clara Convention Center. For a basic introduction to RISC-V see my post RISC-V—Instruction Sets Want to Be Free. It is clear that RISC-V is already becoming dominant in academia since there aren't really any alternatives (x86 and Arm are both too complicated for educational purposes, and too encumbered with lawyers for grad students to build unlicensed implementations). What remains to be seen is just how important RISC-V becomes in the commercial sector. There have been a couple of high profile "wins". NVIDIA has said that all their chips will contain a RISC-V control processor. Western Digital has said that all their chips will switch to RISC-V. To put it in a succinct question: Is RISC-V like Pascal or Linux? Pascal was tremendously influential in the teaching of computer science, but not really used in industry. Linux started with zero credibility but eventually killed off all other server operating systems. To me, this is the biggest question in computer architecture today. Meanwhile, the semi-annual RISC-V workshops have grown and now morphed into the first RISC-V Summit occupying the Santa Clara Convention Center (previous workshops borrowed auditoriums from companies like Google or Western Digital). The conference proper will be on December 4th and 5th. As always, there are intriguing presentations by companies who may or may not be working on stuff behind the scenes: Google, Qualcomm, Facebook, and VMWare are all presenting at the summit. Agenda Tuesday key sessions: Krste Asanovic (of UC Berkeley and SiFive) RISC-V State of the Union . Martin Fink (CTO of Western Digital) Unleashing Innovation from Core to Edge . Patrick Johnson (VP Mixed-Signal and FPGA of Microchip) Enabling the Freedom to Innovate. Robert Shearer (Director of Silicon Architecture and Modeling of Facebook) The 100X Problem—How to Redefine Silicon for Augmented Reality . Wednesday key sessions: Dave Patterson (of UC Berkeley, Google, and Vice-chair of the RISC-V foundation) A New Golden Age for Computer Architecture: History, Challenges, and Opportunities . Yunsup Lee (CTO of SiFive) Opportunities and Challenges of Building Silicon in the Cloud . Rob Oshana (VP Software Engineering of NXP) Deepening the RISC-V Ecosystem to Drive Industry-Wide Adoption . Michael Gielda (VP Bizdev of Antmicro) Accelerating Innovation: Why Google's TPU Was Just the Start . Greg Wright (Senior Director of Engineering of Qualcomm) RISC-V: Opportunities and Challenges in SoCs. That takes us up to lunch each day. In the afternoon there are various presentations and panel sessions running in parallel. Ones that intrigues me especially, just from the titles (and the companies) are: Analyzing the Disruptive Impact of Access to Silicon Technology by Andreas Olafsson, a program manager at DARPA. Explore How to Integrate RISC-V to Build an Open Common Automotive Platform by Tiejun Chen of VMWare. If We Get RISC-V Security Right, It Will Become the Dominant Processor in the $470B IoT Market by Jothy Rosenberg, CEO of Dover Microsystems. The Esperanto ET-Maxio High-Performance Out-of-Order RISC-V Processor by Polychronis Xekalakis and Chris Cello of Esperanto. Never Again: Spectre-Proofing Chip Designs with End-to-End Formal Methods by Adam Chlipia of MIT. How to Protect RISC-V Against Side-Channel Attacks? by Elke de Mulder and Michale Hutter of Rambus (presumably the cryptology division). There's More There is an exhibition open from 10am to 7pm on Tuesday (there is a reception in the exhibit hall that evening), and from 10am to 3.30pm on Wednesday. There is a training day on Monday, and a day for members of the RISC-V foundation on Thursday. Also, an opening reception on Monday evening. Want to Attend? Details of the summit, including a link to register, is on the RISC-V Foundation's website. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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