Cadence Encounter® Test uses breakthrough timing-aware and power-aware technologies to enable customers to manufacture higher quality, power-efficient silicon, faster and at lower cost. Encounter Diagnostics identifies critical yield-limiting issues and locates their root causes to speed yield ramp. Encounter Test is integrated with Encounter RTL Compiler global synthesis and inserts a complete test infrastructure to assure high testability while reducing the cost-of-test with on-chip test data...(read more)![]()
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