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Designer View: SoC Interconnect Analysis – What We’re Doing, What’s Still Needed
Many products and methodologies are available for block-level verification, but system-on-chip (SoC) interconnect analysis is not so well served. At a recorded Cadence Theater presentation at the 2013...
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Wide I/O 2, Hybrid Memory Cube (HMC) – Memory Models Advance 3D-IC Standards
Memory models are essential for SoC verification, and this week (August 6, 2013) at MemCon, Cadence is announcing the industry's first memory models for five emerging standards. This blog post provides...
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What's Good About RF PCB Libraries? 16.6 Has a Few New Enhancements!
There have been a few new library level enhancements made to 16.6 Allegro RF PCB Editor—New librariesSetup enhancementsDRC removal for netlist re-importDiscrete library translator enhancementsRead on...
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Semiconductor Memory Challenges Will Be Overcome, MemCon Keynoter Says
SANTA CLARA, Calif.--Just a few hundred yards from twisting and turning amusement park roller-coasters, Martin Lund took his audience on another thrill ride on Tuesday morning: a journey through the...
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MemCon Samsung Keynote: New DRAM and Flash Memory Architectures are Needed
Want to know what Samsung is thinking about the future of DRAM and NAND Flash memory technology? That all became clear at an informative and entertaining keynote speech at the MemCon conference August...
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Discover Programmable MBIST and Boundary Scan Insertion and Verification...
Cadence Encounter® Test uses breakthrough timing-aware and power-aware technologies to enable customers to manufacture higher quality, power-efficient silicon, faster and at lower cost. Encounter...
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3D-ICs; Marvelous Memories; EE, Heal Thyself (Great Reads 8-9-2013)
All the news that's fit to blog about this week. 3D-ICs: Semiconductor Hype?It's almost always hard to tell at the beginning of an adoption cycle what's real and what's not. The optimists wax lyrical,...
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MemCon Panel: Promises and Pitfalls of 3D-IC Memory Standards
Much has been said about a "memory wall" that emerges when the throughput needs of the system outstrip the performance of the memory. One possible solution is to leap right over that wall with...
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Scaling the Semiconductor Memory Wall
SANTA CLARA, Calif.--If you're concerned about the semiconductor memory wall and its impact on electronic system design, don't be.The semiconductor memory wall is about to be knocked down, and now the...
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What's Good About AMS Schematic Undo? It’s in the 16.6 Release!
Just a very brief post this week on a new AMS Simulator (PSpice) capability.The AMS Simulator 16.6 release allows you to undo schematic changes after you’ve done a netlist and simulation.Read on for...
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Virtuosity: 16 Things I Learned in July by Browsing Cadence Online Support
Feeling a bit lazy this month, but even without digging too deeply, I could find 16 new and interesting bits of content...Application Notes1. Adding and Managing CDF Parameters for Fluid Guard Rings...
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Getting Ready for ESL with Emulation!
Next week on Monday, August 19 th , Gary Smith will run a webinar called " ESL - Are You Ready? " Atrenta's Mike Gianfagna, fellow co-blogger Jason Andrews, and I have had discussions with Gary since...
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Flash Memory Summit: What’s Driving 3D NAND Flash, What Challenges Remain
How will NAND Flash memory scale as semiconductor process nodes dip below 20nm? The best combination of cost, power and performance will be found in 3D NAND architectures, according to panelists at a...
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Enhance Your Packaging Documentation Outputs with the New SKILL Spreadsheet...
Spreadsheets, we all use them, and many of us do so daily. They are an efficient means of communicating information quickly. But, they are far more powerful if you can format them with colors, fonts,...
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Coolest System Design—Ever (Great Reads 8-16-2013)
Here are a few things that caught my eye this week. How clever is that??In the evolution of a design, there comes a point where functionality, cost, performance, and other aspects are pretty much...
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Designer View: New Emulation Use Models Employ Virtual Targets
AMD has been using emulation for IC design for many years, but engineers there have recently found two new ways to use this versatile technology. At a recorded Cadence Theater presentation at the 2013...
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Gary Smith Webinar: “The True ESL Flow is Now Real”
EDA analyst Gary Smith (right) has been advocating electronic system-level (ESL) design since 1997, and he has just declared that the industry finally has a "true" ESL flow. In an archived August 19...
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Bob Pease PCB; Secret Smart Watch; ESL Lives! (Great Reads 8-23-2013)
Out in the big wide world, there's continuing turmoil in the Middle East, Mark Zuckerberg wants universal Internet access for all, and watch pitchwoman Maria Sharapova is out of the U.S. Open Tennis...
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MemCon 2013—Keynote, Panel, and Session Proceedings Available
The MemCon 2013 conference, held August 6 in Santa Clara, California, provided a comprehensive overview of the past, present, and future of semiconductor memory technology. Nearly 500 attendees came to...
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Book Review: An “Expert Guide” to Multicore Embedded Systems
If you're going to be working on any aspect of multicore embedded system design—be it systems architecture, SoC development, or software programming—a newly published book titled Real World Multicore...
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