If you're staring out at the world of semiconductor memory IP and wondering how to make heads or tails of it, you've got sympathetic company. And yes, for electronics systems design engineers, it does seem like controlled chaos out there.
But Cadence offered a little clarity this week with a live, online panel moderated by Tom Hackett, Cadence Product Marketing Director and an expert on verification IP who has written extensively about these challenges. On the panel were:
- Wendy Elsasser, a DDR IP architect at Cadence, who has more than 15 years of experience in design and architecture of SoC subsystems
- Kishore Kasamsetty, Cadence product marketing director, who focuses on memory design IP
- Scott Jacobson, senior product marketing manager at Cadence, who focuses on the memory model portfolio and Ethernet protocols
- Robert Adams, director of the Cadence R&D Memory Model team
The chat quickly grappled with one of the major issues of the day: rapidly changing memory protocols. Take LPDDR, which is now up to LPDDR4 in its evolution.
Elsasser walked the audience through the differences in each generation, ending with design challenges involving the two most recent, LPDDR3 and 4:
She chatted:
"The increasing speeds of LPDDR3 and LPDDR4 generate new design challenges. Power management in the SoC is critical to minimize system power. The SoC must manage tradeoffs between power and high-frequency operation."
The panel also tackled Wide I/O, Hybrid Memory Cube (see image, right), and DDR 4 as well as verification challenges and opportunities for each.
I won't spoil the fun. Please check out the complete chat and let us know what topics you'd like us to schedule chat sessions for in the future.
Brian Fuller
Related stories:
--Wide I/O 2, Hybrid Memory Cube (HMC) – Memory Models Advance 3D-IC Standards
--Semiconductor Memory Challenges Will Be Overcome, MemCon Keynoter Says
--Scaling the Semiconductor Memory Wall