Clik here to view.
Should More Semiconductor, EDA Startups Look to Kickstarter?
Unless you've been trekking in the Himalayas the past decade, you've noticed a big change in the nature of semiconductor and EDA startups. (And if you have been out wandering, welcome back! There's...
View ArticleClik here to view.
Clarifying the Changing Semiconductor Memory IP Landscape
If you're staring out at the world of semiconductor memory IP and wondering how to make heads or tails of it, you've got sympathetic company. And yes, for electronics systems design engineers, it does...
View ArticleClik here to view.
Five-Minute Tutorial: EM Model Files Revisited
Back in January, I posted a Five-Minute Tutorial about creating EM Model files. We'll be referencing this previous post a lot, so check it out quickly right now.That method has worked well for me, but...
View ArticleClik here to view.
IEEE 802.3 -- Standardizing the Next Generation of Ethernet PHYs
I attended the IEEE 802.3 standards meeting in York, England recently. Over 200 people came from all over the world to work on standards for the next generation of Ethernet products.Work is ongoing to...
View ArticleClik here to view.
Export Compliance Regulations: Devil’s in the Details
SAN JOSE, Calif.--Lend your smartphone to a friend, go to jail. Well, it's not quite that drastic, but if that friend is a foreign national, the very act of handing that phone over can violate U.S....
View ArticleClik here to view.
Agilent splits; Great Pease's Ghost; India fabs (Great Reads 9-19-2013)
The fall has turned into its usual frenzy of activity, and so, trying to improve the signal-to-noise ratio this week, we find....SplitsvilleHewlett-PackardAgilent announced this week it was splitting...
View ArticleClik here to view.
Recorded Presentation Introduces Tensilica Dataplane Processors
I did not attend the 30-minute talk on "Customizable Processor Basics" given at the Design Automation Conference by Chris Rowen, Tensilica founder and now Cadence fellow. It was not due to lack of...
View ArticleClik here to view.
Intel Developer Forum (IDF13): A "Look Inside" the Technology Showcase
The recent Intel Developer Forum 2013 in San Francisco was notable for the sheer number of attendees and the broad spectrum of the technology industry they represented.Intel's embrace of a more...
View ArticleClik here to view.
What's Good About ADW’s Pull-Down Lists? 16.6 Has a Few New Enhancements!
The 16.6 Allegro Design Workbench (ADW) release now provides the ability to customize the pull-down list values for part property editing. Some classification properties require “freeform” values...
View ArticleClik here to view.
TSMC 3D-IC Reference Flow Supports 3D Die Stacking
An important milestone for any new semiconductor technology is the availability of a foundry EDA reference flow. Such a milestone occurred last week (Sept. 18, 2013) as Cadence and TSMC delivered the...
View ArticleClik here to view.
Tackling Complexity at the System-to-Silicon Verification Summit
System-to-silicon verification is the biggest challenge our industry faces today. It's also the biggest opportunity for both design teams and EDA vendors. Consider the productivity and time-to-market...
View ArticleClik here to view.
ARM TechCon Panel: Embedded Software Development Goes from Isolation to...
Not long ago embedded software engineers worked in isolation, with no standards, no common platforms, nothing reusable for future projects, and no collaboration with any other company. A collaborative...
View ArticleClik here to view.
What's Good About FPGA System Planner and Netgroups? 16.6 Has It!
Beginning with the 16.6 SPB release, FPGA System Planner (FSP) can create net groups automatically whenever an interface is instantiated or a protocol is created. These switches control the...
View ArticleClik here to view.
ARM TechCon: New Network Means New Electronics Design Demands
SANTA CLARA, Calif.—It's a rare moment when you can see the train wreck coming and the collision-avoidance potential at the same time.We're at a moment like that now in electronics design.This occurred...
View ArticleClik here to view.
Voltus – Massive Parallelism Speeds Power Integrity Analysis and Signoff Closure
Performance, capacity, accuracy. These are the three criteria that IC design teams want most in a power analysis solution. By using a massively distributed, parallel compute engine along with a...
View ArticleClik here to view.
RTL Compiler Beginner’s Guides Available on Cadence Online Support
With shrinking design nodes, a significant portion of the delays are contributed by the wires rather than the cells. Traditional synthesis tools use fan-out-based wire-load models to provide wire delay...
View ArticleClik here to view.
High-Level Synthesis—What Expertise Is Needed for Micro-Architecture Tradeoffs?
My most recent blog post mentioned how utilizing new algorithms together with high-level synthesis can continue to drive innovation in hardware design by balancing power consumption with performance...
View ArticleClik here to view.
Semico Panel on Semiconductor IP Ecosystem: Reducing Cost and Risk
Despite years of progress in both business models and technology, semiconductor intellectual property (IP) is still risky, costly, and difficult to integrate. Can the IP ecosystem relieve the pain...
View ArticleClik here to view.
Semiconductor Companies’ Big Squeeze
SAN JOSE, Calif. – Call it the rumblings of re-verticalization in the electronics industry. Call it the Semiconductor Sandwich. Call it whatever you like, but semiconductor companies are experiencing a...
View ArticleClik here to view.
11 Things I Learned by Browsing Cadence Online Support
I guess by now most of us are already familiar with Rapid Adoption Kits (RAKs). These are packages that include a detailed instructional document and a lab database. You can browse all the available...
View Article