With shrinking design nodes, a significant portion of the delays are contributed by the wires rather than the cells. Traditional synthesis tools use fan-out-based wire-load models to provide wire delay information, which has led to significant differences in quality of results (QoR) between the "synthesis" and "implementation" tools. RTL Compiler Physical (RCP) as a tool allows the user to integrate the "physical" information much earlier in the flow, and this provides...(read more)![]()
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