The design and physical implementation engineers involved in early to late stage synthesis require a flow that helps them investigate timing using a structured and physically aware approach. Cadence Encounter® RTL Compiler (RC) Timing Analyzer was developed to address exactly this need. It can be used in conjunction with multiple physical GUIs allowing physically aware timing debug analysis of a design in RC through a global view of the overall timing challenge, and via user-configurable dynamic...(read more)![]()
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