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Whiteboard Wednesdays - What is VIP?
Today, our continuing Whiteboard Wednesdays video blog series will provide an overview of Verification IP and how it helps test today’s complex SoCs.Watch this week's episode to hear Tom Hackett,...
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e Language Editing with Emacs
Specman and e have been around for a while, and some clever people have developed a nice syntax highlighting package for Emacs. What does this package do? Well, have a look yourself: Editing in Emacs...
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ISSCC: Perspectives on System-Design Evolution
Last week, we checked in with Cadence fellow Chris Rowen to get a perspective on some higher level trends in the evolution of electronic system design. This week, the annual ISSCC conference is...
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Improve Design Quality with Adjacent Layer Object Avoidance in the 16.6...
In this week's discussion, let's take a look at a cornerstone of every good substrate design: plane shapes and voiding. In particular, what do you do if you need to void around an object on one or more...
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What Your Circuit Doesn't Know, Can Kill It!
Device variation has been a long-standing problem in custom design. Over the years, our customers have made many attempts to model the behavior though parameterization, simulation model extensions,...
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Microprocessors' Future; Innovation Gap; AMD's ARM Chip: Electronics Week in...
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RTL Compiler (RC) Timing Analyzer (RTA) Flow
The design and physical implementation engineers involved in early to late stage synthesis require a flow that helps them investigate timing using a structured and physically aware approach. Cadence...
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DesignCon 2014: What Comedian Henny Youngman Can Teach Signal Integrity...
Patient: Doctor, it hurts when I raise my arm.Doctor: Well, don't raise your arm!From the 1930s to the 1980s, comedian Henny Youngman was famous for his "one liner" jokes. But the joke above is not...
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Whiteboard Wednesdays - Implementing Always-On Audio
In this week’s Whiteboard Wednesdays episode, Gerard Andrews, from the Tensilica Audio DSP Group at Cadence, discusses always-on audio functionality. Gerard details features like voice trigger, sensor...
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How Cadence Acquisition of Forte Boosts High-Level Synthesis
When you're in a rapidly expanding marketplace that is coming into mainstream adoption, you want to have the most complete solution possible. And that is some of the thinking behind the Cadence...
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Multi-Fabric Planning for Efficient PCB Design
Recently, an article was published in Printed Circuit Design and Fab by Cadence product manager Kevin Rinebold talking about Multi-Fabric Planning for Efficient PCB Design(see page 22 of printed...
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Why Cadence Exhibits at Mobile World Congress and CES 2014
Longtime EDA industry editor Peggy Aycinena posed an interesting question with a blog post titled "CES 2014: Why was Cadence there?"She noted that ARM has a presence at CES:"But Cadence? Why would they...
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New Incisive vManager Keeps Functional Verification Costs in Check
Functional verification costs are skyrocketing at 40nm and below, and the only solution is to dramatically increase verification productivity. Cadence this week (Feb. 24, 2014) is responding with the...
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Curtain Lifts on Mobile World Congress 2014
BARCELONA, SPAIN--Start with an astonishingly lovely city. Add in about 70,000 electronics-crazy attendees; stir in some jet lag, Sangria and paella, and you have Mobile World Congress 2014. The...
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Whiteboard Wednesdays - How the MIPI Alliance Works to Enhance Mobile Devices
In this week's Whiteboard Wednesdays episode, Moshik Ruben, Product Marketing Director at Cadence, highlights the MIPI Alliance's focus on standardization to help improve today's mobile devices. Moshik...
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Incisive vManager at DVCon - Come See It!
Have you heard the news? There is a new version of vManager announced this week, right in time for DVCon. vManager has been completely re-architected to be a database driven environment, scaling to...
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Whiteboard Wednesdays Video Blogs – How to Succeed with Semiconductor IP
There really is a whiteboard in the new Cadence Whiteboard Wednesdays video blog series, and it's put to good use. This new blog series provides practical information and hands-on insights about...
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What's Good About DEHDL’s Cross Referencing of Hierarchical Nets? 16.6 has...
The 16.6 Design Entry HDL (DEHDL) Cross Referencer has some new enhancements to report on hierarchical nets.Read on for more details …Just a quick post this week to share with you a couple new...
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Resetting Your UVM SystemVerilog Environment in the Middle of a Test —...
In general, reset will be applied at different times within a test. 1. Reset at the beginning of a testIn a typical UVM test you might start out by applying a reset, and then go on to configure your...
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Embedded World 2014: The Design Challenges Ahead
NUREMBERG, GERMANY--It is, in the electronics world, a singular show in a singular place. Embedded World combines scores of companies with a broad range of electronics technologies and thousands of...
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