Recently, an article was published in Printed Circuit Design and Fab by Cadence product manager Kevin Rinebold talking about Multi-Fabric Planning for Efficient PCB Design(see page 22 of printed magazine).
Today's BGA-style packages have a significant impact on PCB layer count, route complexity, and cost. Efficient BGA net assignment and patterning of power and ground pins can make the difference between a four- and a six-layer PCB. Historically, there's been minimal visibility or consideration of the PCB during package net list development, which itself is a direct function of the I/O pad ring layout of the chip. In addition to the layer count and cost, performance margins of high-speed, high-bandwidth interfaces can no longer accommodate poor pin assignments and overly complex routing schemes. The good news is there are new methodologies and tools that enable the necessary coordination and multi-fabric visibility to properly plan and manage these challenges.
The article presents a methodology for PCB-influenced die/package planning of cross-fabric interfaces showing the relationship to PCB layer count and complexity. It explores the relationship between the I/O pad ring, die bumps, package ball pads, and critical devices on the PCB. It discusses techniques to optimize connectivity across these elements along with the role of route feasibility to validate pin assignments. Routing tools and methods to address the complexity of high-performance interfaces like DDR4 or PCIe 3.0 are also covered at both the package and PCB level. Finally, the article touches upon data exchange and communicating design intent when working with external resources or geographically diverse design teams.
Read the full article and tell us about your experiences of using multi-fabric planning methodology!
Team Allegro