Last week, Professor Jan Rabaey of the University of California at Berkeley gave a great keynote at Cadence's Low Power Technology Summit that called for changes to the conventional solutions for power reduction. One of the points he made was that today's designs are over-designed and over-constrained with additional margin. One of the reasons is variability -- which results in the creation of timing margins to ensure that process variability or environmental conditions do not cause the chip...(read more)![]()
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