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Packed House Expected for Cadence Low-Power Technology Summit
It looks like it might be standing room only for latecomers to the Low-Power Technology Summit at Cadence headquarters building 10 auditorium this Thursday (18 October). Registration has been very...
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TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs
TSMC, the world's largest semiconductor foundry, is thinking big when it comes to next-generation process technology. At the TSMC Open Innovation Platform (OIP) Ecosystem Forum Oct. 16, TSMC described...
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Do you MOOC? Expanding Access to e (IEEE 1647) Verification Training Globally
Two of the key factors for successful and productive simulation-based hardware verification are a efficient verification language and an associated methodology. As the global design and verification...
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Press Release About TSMC Flow, Blog from ARM Validate Cadence’s Mixed-Signal...
A press release and a blog post caught my attention this week (October 15, 2012), and they have clearly demonstrated Cadence's leadership in 20nm process nodes and mixed-signal solutions. The press...
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Jan Rabaey Keynote: For Lower Power, Re-Think Computing
If we want truly energy-efficient servers and mobile devices, existing low-power design techniques are not sufficient, according to Jan Rabaey, professor of electrical engineering and computer science...
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Cadence at ARM TechCon – Verification IP, 28nm Digital, Low Power, Mixed...
With nine technical paper presentations, two sponsored sessions, demos, and exhibits, Cadence will have a strong presence at ARM TechCon in Santa Clara, California Oct. 30-Nov. 1, 2012. Cadence papers...
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What's Good About Allegro PCB Editor Stipple Highlighting? See for Yourself...
The 16.5 Allegro PCB Editor now has the added ability to accentuate objects and layers in Allegro PCB Editor by providing pattern support. Read on for more details …Stipple pattern support is provided...
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Margins are Costly - Don't Let Them Grow Out of Control!
Last week, Professor Jan Rabaey of the University of California at Berkeley gave a great keynote at Cadence's Low Power Technology Summit that called for changes to the conventional solutions for power...
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Q&A: TSMC R&D VP Cliff Hou Discusses 20nm, CoWoS Multi-Die Packaging, and...
The recent TSMC Open Innovation Platform (OIP) 2012 Ecosystem Forum marked the release of 20nm and chip-on-wafer-on-substrate (CoWoS) reference flows, as well as new insights about the giant foundry's...
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Event Report: Club Formal San Jose – Features and Techniques for Experts,...
Last week over 35 power users from over a dozen companies came together for the latest installment of "Club Formal" -- a user group meeting exclusively focused on topics in formal analysis and...
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Ubuntu 12.10 on a Virtual Platform at ARM Techcon
Next week (Oct. 30-Nov. 1) ARM TechCon 2012 is at the Santa Clara Convention Center. As always, Cadence will be at the conference and exhibit, but I would like to especially recommend one paper for...
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Panelists: Low Power Design Needs System-Level Boost
When low-power design experts get together, much of the conversation turns to the system level. At least that was the case at the recent Low Power Technology Summit held at Cadence Oct. 18, 2012, where...
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Recent Events Show That Customer Interest in Mixed-Signal Remains High
The well attended Mixed-Signal Technology Summit last month really demonstrated the tremendous interest our customers have in learning new methodologies and techniques for mixed-signal designs. I would...
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What's Good about the SPB 16.6 Release? Exciting Features To Improve Design...
The SPB 16.6 Release is available! You can download it from the Cadence Software downloads site.Here are just a few press announcements on the 16.6 release –New Allegro 16.6 Release Accelerates Timing...
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How many cycles are needed to verify ARM’s big.LITTLE on Palladium XP?
At the recent CDNLive! India user conference, Deepak Venkatesan and Murtaza Johar representing ARM India gave a fascinating presentation called "Verifying big.LITTLE using the Palladium XP". Registered...
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ARM TechCon: Inside Story of a 14nm FinFET Tapeout
The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon...
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ARM TechCon: Design at 14nm (or 10nm) – What’s Going to Change
The next semiconductor process node after 20nm promises tremendous power and performance benefits, but also poses some new challenges, according to a presentation by ARM and IBM at the ARM TechCon...
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Video: Cadence VP Tom Beckley Discusses Advanced Node Custom/Analog Challenges
Any discussion about advanced node (below 28nm) that focuses only on digital design is missing an important part of the story. Custom/analog design must be considered too, and that's the subject of a...
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Creating Custom File Systems and the Linux Loop Device
A few weeks ago we had a crisis at our house. My son managed to delete the data from my daughter's USB memory stick. Not only did he delete it, but he did it in such a strange way I have no idea what...
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What's Good About Allegro PCB Editor Component Alignment? See for Yourself in...
The Component Alignment feature is available in Placement Edit Application mode. It was introduced in the Allegro PCB Editor 16.3 release and now enhanced in 16.6 to support the following new...
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