Want to see what Cadence has been up to recently in IP? Register for the upcoming TSMC 2014 Technology Symposiums. You'll find Cadence in Booth #613 at the San Jose event on Tuesday, April 22. We'll also be at the Boston TSMC Symposium on April 29 and in Austin on May 1.
See the full suite of Cadence® tools and IP in action in San Jose:
- Certified Encounter® digital implementation flow for TSMC 16nm FinFET process
- Custom/mixed-signal flow for 16nm FinFET technology
- Extensive portfolio of leading-edge, silicon-proven IP
- Virtuoso® 12.1 flow: comprehensive solutions for 16nm FinFET custom design
- Standard and multi-bit cell characterization at advanced nodes
- Advanced RF analysis technologies in Spectre® RF Simulation Option
- TSMC-certified 3D-IC reference flow
- Comprehensive, foundry-qualified signoff portfolio for FinFET process
Visit the Boston and Austin events to learn more about:
- Comprehensive, foundry-qualified signoff portfolio for FinFET process
- Extensive portfolio of leading-edge, silicon-proven IP
Cadence provides end-to-end design and development solutions for advanced nodes and high-performance cores. Join us as we showcase our leading solutions for TSMC technologies in the areas of IP, mixed signal, design for manufacturing, signoff, characterization, advanced nodes, and 3D-IC. Visit our table for demonstrations of our technologies for IP and advanced design tools.
TSMC Technology Symposium is geared towards engineers, engineering managers, and executives who want to learn more about Cadence collaborations with TSMC.
Get the overview on all of these TSMC events at the TSMC Technology Symposium web site.
Paula Jones
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