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Whiteboard Wednesdays - How IP Enhances Hosted Virtual Desktops
In this week’s Whiteboard Wednesdays, Charles Qi introduces an emerging new application called Hosted Virtual Desktop, which supports increasingly mobile workers who want to use any smart, connected...
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What's New(-ish) in ADE XL in IC 616 ISR 3?
Development Model for ADE and ViVAVirtuoso Analog Design Environment (ADE) and ViVA follow a development model that allows new content to be added in every third ISR. These content ISRs receive...
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What's Good About Capture’s Auto Part Reference? 16.6 has a Few New...
The 16.6 release of OrCAD Capture has a couple new productivity enhancements centered around how reference designators are assigned to components in the schematic.Read on for more details …Design Level...
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Virtuosity: 15 Things I Learned in March 2014 by Browsing Cadence Online Support
Highlights for this month include lots of useful Physical Verification System (PVS) appnotes and several blog articles on advanced analyses and flows in Analog Design Environment (ADE) GXL.Application...
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Multi-Fabric Planning for Smarter Design: Q&A with Kevin Rinebold
With nearly a quarter-century of experience in the IC packaging and co-design markets, Kevin Rinebold (pictured below) has a perfect perch from which to discuss issues and trends in board design. One...
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Keynote: EDA “MOOC” Opens Door to a Planet of Talent
Participants at the recent CCC/SIGDA Workshop on Extreme Scale Design Automation discussed various ways to motivate students to consider EDA-related careers. And few approaches have cast a broader net...
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See Cadence IP Up Close at the TSMC Symposiums
Want to see what Cadence has been up to recently in IP? Register for the upcoming TSMC 2014 Technology Symposiums. You'll find Cadence in Booth #613 at the San Jose event on Tuesday, April 22. We'll...
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Learn Logic built-in self-test (LBIST) macro generation and insertion at your...
Cadence offers a new Rapid Adoption Kit for logic built in self test tasks....(read more)
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EDPS 2014 Keynote: What Intel Needs from Pre-Silicon Prototyping
Pre-silicon prototyping is a new technology for many companies, but at Intel, it's important enough to warrant a dedicated support team. At the Electronic Design Process Symposium (EDPS 2014) on April...
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Keeping Your Circuit in Tune: Sensitivity Analysis and Circuit Optimization
Anyone who has ever played a musical instrument knows how hard it can be to keep the instrument in tune when subjected to variations in weather conditions. Heck, in 2009, Yo-Yo Ma and friends (sorry,...
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The Road to 1 Million Tapeouts
MONTEREY, Calif.--One million tapeouts a year. When Cadence Senior Vice President Martin Lund uttered those words with a smile on his face, the small crowd at an industry event here chuckled knowingly....
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Whiteboard Wednesdays - Taking Command of MIPI PHYs
In this week's Whiteboard Wednesdays installment, Kevin Yee discusses what it means to "take command of MIPI PHYs". This is a first of a three-part series on the topic. Here, Kevin will introduce you...
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New Memory Estimator Helps Determine Amount of Memory Required for Large...
Hi Folks, A question that I've often received from designers, "Is there a method to determine the amount of memory required before I submit a job? I use distributed processing and need to provide an...
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Broadband SPICE -- New Tool for S-Parameter Simulation in Spectre RF
Hi All, Here's another great new feature that I've found very helpful... Broadband SPICE is a new tool for S-parameter simulation in Spectre RF. In the MMSIM13.1.1 ( MMSIM13.1 USR1) release (now...
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TSMC Symposium: EDA/IP Ecosystem Primed for 16, 10nm Nodes
SAN JOSE, Calif. -- 28nm may still be considered the mainstream node, but for leading-edge designers, there is a clear and compelling path from there through 16nm and into even the 10nm design...
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EDPS 2014: Creative Ways to Use Pre-Silicon Prototyping Platforms
A session on pre-silicon software development platforms at the Electronic Design Process Symposium (EDPS 2014) in Monterey, California on April 17 revealed the incredible versatility of these...
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2014 TSMC Technology Symposium: Full Speed Ahead for 16nm FinFET Plus, 10nm,...
Advanced-node semiconductor technology is getting much more complex and challenging, but that isn't slowing things down at TSMC, the world's largest pure-play foundry. At the 2014 TSMC Technology...
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What’s New in Virtuoso ADE XL in IC616 ISR6?
In a previous post, I explained the release model used for Virtuoso ADE and ViVA and listed some of the new features that were available in Virtuoso ADE XL in 616 ISR3. Here are more new features that...
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What's Good About Allegro AMS Simulator PSpice Model Encryption? It’s in the...
With the 16.6 Allegro AMS Simulator (PSpice) release, you now have a new AES 256-bit encryption algorithm. This makes the encryption utility of PSpice and the Model Editor both faster and more robust....
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Whiteboard Wednesdays—Wireless Transceiver Implementations
In this week's Whiteboard Wednesdays installment, Priyank Shukla highlights wireless transceivers and protocol standards 802.11x and LTE/LTE-A. Wireless transceiver implementation options consisting of...
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