SAN FRANCISCO--Electronics system design teams need to discard old ways of thinking, be creative, and work more collaboratively if the industry is to deliver on the promises of advanced node technology, TSMC's R&D vice president said.
"The
conventional wisdom that led to our success in the past will no longer work in the
future," said Dr. Cliff Hou, during his keynote at the 51st Design Automation
Conference here. 
By way of example, Hou (pictured) said:
"We need to work in a concurrent way between EDA and processes. EDA cannot wait until a process is ready to start development. Similarly, process rules can't be set without considering all EDA requirements in the future."
Hou outlined a vision for the evolution of advanced nodes from 20/16nm down to below 10nm that emphasized partnership and innovation during his hour-long presentation at the Moscone Center June 2.
At 20/16nm, for example, EDA vendors are working to solve the coloring issue required because of double patterning lithography.
"If you don't design your process node carefully, easily you can lose one fin," Hou said. Losing one of four fins (25%) means a major design hit, he said. "You have to make sure all the design steps are using coloring; otherwise, the whole flow is broken," he added.
In a presentation earlier this year at the TSMC Technology Symposium, Hou described the company's two current 16nm offerings -- 16nm FinFET (16FF) and 16nm FinFET Plus (16FF+). The "plus" line is a second-generation FinFET technology that provides power, performance, and area advantages.
As Hou looked ahead to 10nm and beyond, he looked back briefly, saying,"We've done a pretty good job in the last decade." At 10nm and below, "I think from a process point of view, we can provide PPA (power, performance and area) improvements but development costs will be high. We have to find the best solution. Every penny will count at 7 and 10nm."
Deep Dive
At that earlier presentation, Hou said TSMC is actively working on 10nm. Early customer engagements are underway, tapeouts are expected in 2015, and risk production is planned for late 2015. The 7nm process node is heading for risk production by mid-2017, and preliminary design rules for early test chips will be available in 3Q 2014.
What else did Hou see in his DAC keynote technological crystal ball? Lithography, Hou said, will lean on immersion technology for as long as possible. TSMC is also considering directed self-assembly as an option at 16nm half pitch.
FinFETs will probably be useful to the 7nm node. After that, Hou sees the industry embracing nanowire or gate-all-around structures and perhaps III/V materials to enable supply voltages of half a volt and below. Resistivity is becoming a bigger issue for interconnect at 16 and 10nm, thanks to narrow wires. Design engineers may have to consider different metal pitches to resolve the situation, he added.
He closed by saying:
"With the new challenge at 10nm and beyond, it creates new opportunity for new innovation and new ways of thinking. Whoever has the new idea will win. To keep PPA scaling at 10nm and beyond requires tighter collaboration between process nodes, design, EDA, and IP. The message here is conventional wisdom no longer holds. We need to have a different mindset, a different working model for 10nm and beyond."
Brian Fuller
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