SAN FRANCISCO--There were times-simpler times-when electronics designers toiled in distinct walled gardens: chip, package, and board. But today, interdependencies among those three require those walls to be broken down-not the least of which because blazingly fast speeds are causing havoc with signal and power integrity. These are challenges that require an examination of where gaps might be in the methodologies, an honest conversation about codesign. and a reconsideration of how we structure engineering teams.
That was the take-away from a Cadence-sponsored panel of experts at the 51st Design Automation Conference here. Titled "High-Speed Cross-Fabric Interface Design: It's not 1's and 0's anymore... it's a noisy world," the panel featured:
- Brad Brim, senior staff product engineer with Cadence
- Jenny Jiang, principal engineer of signal integrity and power integrity at Altera
- Xiaoning Qi, engineering manager, Intel Mobile and Communication Group
- Upen Reddy, technical leader, Cisco Enterprise Networking Group
- Dan Weed, director of design solutions at GLOBALFOUNDRIES
Jiang teed up the issues eloquently:
"The challenge is basically that we have to deal with three things at the same time: signal bandwidth, channel density, and the tradeoff of product performance to cost. We don't want to overdesign our products. Packages and boards are no longer conductors; they act like transmission lines with propagation properties that contribute to distortion. When we connect I/O through the package, it's a totally different story. And when we cascade to the board, it's a different story again."
Weed, a longtime industry veteran, added:
"What worked today may not work tomorrow. We are seeing speeds in excess of 28Gbps and we are now having routine discussions about the need for 56Gbps. In this environment, codesign early and codesign often and partnering early are the keys to success."
Over the course of 90 minutes, the panel addressed a broad array of challenges. Here are some of the highlights:
Digital has become analog: How do we deal with this?
Brim said one area where he's seeing that metamorphosis is in high-speed serial interconnect.
"I used to think 40GHz was a big deal. Today, hi-speed interconnect may start out as zeroes and ones but it certainly doesn't end up that way," Brim said.
To address these challenges, some teams use techniques like pre-emphasis and DFE to correct signals "but they're never zeroes and ones," he said. "If you don't have all the DSP processing before the signal and after the signal, it's just noise."
He then described power delivery challenges:
"If you talk about power, now you have power, noise, and jitter. You have noise in your power delivery network and you don't know where it's coming from; then you have additional jitter in your hardware you have to deal with."
Brim noted that some teams are "undeconsidering" power integrity in high-speed serial with the additional jitter that it causes.
"It causes signal integrity issues because your signal is always referenced to VSS or ground, and if you've got noise in power delivery network that directly translates into noise in your signals. Vias are an area where there's an extremely strong coupling between signals and power."
Added Weed:
"We have to take that eye, that wave, that unknown, that gray space between ones and zeroes and convert it back to ones and zeroes to do digital processing that we have to do. That's the goal at the end of the day. All this has to be done with the challenge of time to market and cost and performance tradeoffs and hitting the application space before your competitor does."
Methodology evolution
As teams grapple with complexity, the need for co-design becomes greater, to intelligently and productively deal with technical issues but also to get to market sooner.
Said Qi:
"I'm quite passionate about co-design. In today's environment you cannot isolate silicon design, package design, and platform design. So the silicon platform co-design is something people are aware of. We need to look at the platform and how it affects silicon design. On other hand, more importantly, it is electrical validation and debug. SoC and system debug without knowledge about the silicon design cannot be effective. You have to look into the whole thing together in your electrical validation."
Acknowledging that he sometimes gets the impression that people think he just wants to sell them three sets of tools, Brim said:
"If I were to stand up and tell you "do codesign or you can't get your job done", that's not right either ... because you have different analysis technologies that work between package, board versus IC-type extractions. So you have to design individual fabrics in different tools, but you have to design across multiple fabrics at the same time."
An audience member asked the panelists to identify gaps in the current methodology. Jiang said the industry needs better metrology and sophisticated 3D extraction tools because some existing methodologies are too time consuming or don't offer sufficient accuracy.
Teamwork
These challenges also require a reconsideration of design team organization, especially if codesign is the objective.
Qi said he used to manage the signal integrity team. "There was traditionally no PI; just SI," he said. "What I try to emphasize is integrating these." And in optimal situations such structures would include at least one engineer who has worked in both PI and SI to help bridge the discipline divide, he added.
Looking forward as speeds increase to 112Gbps, a different way of thinking will need to emerge again, according to Reddy. At that point, he said, the industry may need to look at different signaling schemes, such as the quadrature-amplitude modulation (QAM).
"I want to see codesign start to include them, and even optical design," said Reddy.
Brian Fuller
Related stories:
-- Multi-Fabric Planning for Smarter Design: Q&A with Kevin Rinebold
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