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Implementing User-Defined Register Access Policies with vr_ad and IPXACT
The register and memory package vr_ad for Specman is used in pretty much every verification environment. In most cases today, the register specification is captured in an IPXACT description and the...
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IP Talks! Keynote at DAC 2014—Rethinking Image Processing in SoC Design
Many systems on chip (SoCs) have a "camera block" or image signal processor (ISP) that takes raw data from an image sensor and manipulates that data. But ISPs are moving away from their traditional...
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Whiteboard Wednesdays - Verifying Solid State Drives Incorporating NVM Express
In this week's Whiteboard Wednesdays, Mukul Dawar explains the NVM Express protocol and considerations to keep in mind when using verification IP to perform functional verification.
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EDA Plus Academia: A Perfect Game, Set and Match
Excuse the tennis analogy, but just coming out of Wimbledon! However, EDA and academia have had a long-standing tennis match, if you will, in which there is a "give and take" between the EDA world...
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What's Your Summer Engineering Project?
You're an engineer, which means you're never really not doing or thinking about engineering. It's now summer and the great thing about summer vacation is you can design and build something for fun and...
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Upcoming Webinar: SoC Verification Challenges in the IoT Age
When it comes to Internet of Things systems, the name of the game is low power and small footprint. This is often easier said than done in an environment in which designers must take those two huge...
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Quantus QRC Extraction Solution – Massive Parallelism Extracts Accurate...
Over the past 14 months Cadence has brought massive parallelism to static timing analysis (Tempus Timing Signoff Solution) and power analysis (Voltus IC Power Integrity Solution). Today (July 14, 2014)...
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What's Good About Allegro PCB Editor Dual-Side Contact Components? It’s in...
The use of dual-sided contact components when placed on internal layers of the PCB allows connections to be made from either side of the device. One of the benefits of using this emerging technology is...
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Whiteboard Wednesdays - See How Customizable Processors Can Help to Offload...
In this week's Whiteboard Wednesdays, we take a little different approach and show you a fun and fast way to understand how Cadence® Tensilica® Xtensa® processors work, and how you can easily use them...
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Ethernet in Cars - The Next Big Thing for Ethernet
Ethernet is coming to cars. Cars now have rear-view cameras and infotainment systems which require video to be transported at a high data rate. Ethernet is the best technology to carry this data....
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EDA Must Think Beyond ICs in Automotive Electronics Market, Panel Says
Automotive electronics in general and autonomous vehicles in particular represent enormous potential for the EDA market, but not in the ways you might be thinking. That was the consensus of a panel of...
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Protium FPGA-Based Prototyping Platform – Speeding Bring-Up Times
FPGA-based prototypes provide excellent platforms for pre-silicon software development - but prototype bring-up times are so long and painful that much of the value is lost. Promising to shorten...
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Sean Dart Q&A: Former Forte CEO Discusses Past, Present, and Future of...
Earlier this year Cadence acquired Forte Design Systems, a pioneer of high-level synthesis (HLS) and provider of the Cynthesizer SystemC-based synthesis tool. Sean Dart, Forte CEO since 2006, is now...
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Whiteboard Wednesdays - Get to Know 802.11a/c Wireless Analog Front End...
In this week's Whiteboard Wednesdays, Priyank Shukla discusses Cadence's wireless analog front end (AFE) solution for 802.11a/c.
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Designer View – Getting the Best Use From Static Low-Power Verification
Do you want assurance that your system-on-chip (SoC) netlists are "power clean?" In a recorded presentation on the Cadence web site, Harshat Pant, principal engineer at Broadcom, shows how static...
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Boosting Design Productivity with Team Design and PTC Windchill: Webinar
For some time now, industry has recognized the need for structured design methodologies that integrate ECAD design with product data management (PDM) systems. We know that creating an electronic...
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DAC 2014 Panel: Chip, Package, and Board Design Must be Reconsidered
SAN FRANCISCO--There were times-simpler times-when electronics designers toiled in distinct walled gardens: chip, package, and board. But today, interdependencies among those three require those walls...
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What's Good About Allegro PCB Editor Multiple Constraint Region Assignments?...
Just a short post today.In the 16.6 Allegro PCB Editor release, multiple region shapes can now be assigned to a single region constraint object. Using the General Edit Application mode, pre-select...
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Archived Webinar – An Introduction to High-Level Synthesis (HLS)
High-level synthesis (HLS) is rapidly entering the IC design mainstream - but how much do you know about this emerging technology? A recently archived Cadence webinar sets the record straight about...
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Incisive Simulation and Verification: Top 10 New Things I Learned While...
Cadence Online Support, http://support.cadence.com, provides access to support resources including an extensive knowledge base, access to software updates for Cadence products, and the ability to...
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