Where are the gaps in 3D-IC design, and how can they best be bridged? In order to provide a cost-effective alternative to silicon process scaling, work is still needed in 3D-IC design tools and methodologies, according to presenters at a recent meeting of the Global Semiconductor Alliance (GSA) 3D-IC Packaging Working Group.
Presenters at the Working Group meeting included the following:
- Jan Vardaman, analyst, Techsearch International
- Brandon Wang, director, 3D-IC solutions, Cadence
- John Ferguson, director of marketing for Calibre, Mentor Graphics (co-presenting with Dusan Petranovic, interconnect modeling technologist, Mentor)
- Bill Martin, vice president of engineering, E-System Design
The Working Group meeting was July 23, 2014 in Sunnyvale, California. Presentation slides are available at the GSA website.
One recurring theme of the meeting was that 3D-ICs involve far more than just throwing several stacked dies into a single package. "Anything introduced in 3D-IC is going to be a new architecture," Vardaman said. "It's way more than stacking existing memory and logic dies together," Wang concurred. "The winning technologies will be those that redefine the architecture."
Analyst View—Where the Gaps Are
Vardaman presented some perspectives from a 3D-IC "gap analysis" her company is working on. The real driver for 3D-ICs, she said, is the high cost of lithography in next-generation technology nodes. "People will stay at the node that is economical for whatever they are doing," Vardaman said. "Until they can put it on a stack, they will put it on an interposer."
Memory stacks with through-silicon vias (TSVs) are here, Vardaman said, and it's important to remember that these devices come with new memory architectures. She noted that Tezzaron is already doing some production shipments, and customers are looking at engineering samples of the Micron Hybrid Memory Cube. Volume shipments will happen in 2015, she said.
Techsearch International is trying to identify areas in 3D-IC design and manufacturing that need additional work. Availability of commercial 3D EDA tools is one concern. "One thing that's really critical is thermally aware design tools, so people can do tradeoffs and see what they can do to manage heat dissipation," Vardaman said. Other needed capabilities are pathfinding, floorplanning, 3D routing and verification, and power/signal integrity and die/package co-design.
Other "gaps" identified by Techsearch include the following:
- Micro-bumping and assembly for stacked die. Higher throughputs and better yields are needed.
- More work on the assembly of die on interposers.
- Wafer thinning, specifically the de-bonding step in the temporary bonding process. Higher yields and higher throughput are needed. Warping is a problem.
- Additional work on thermal design, where logic is part of the stack. New low-power architectures are required, and thermally conductive or insulating materials should be considered.
- Test methodology and solutions. In addition to known-good die (KGD), known-good stacks (KGS) are important.
- Reliability data including drop test data.
- Yield improvements that lower cost.
"All this stuff needs to be done at a co-design level," Vardaman concluded. "IC and packaging people use the term co-design a lot, but it has to be that way because otherwise we don't see this working out. You have to get all the people involved into the same room."
Brandon Wang: Advantages, Challenges, and Design Flows
Wang's presentation was titled, "More than Moore—3D-IC Economics and Design Enablement." He noted that the 3D-IC emphasis is now on heterogeneous integration, and that this kind of integration could be very important in developing the Internet of Things (IoT).This emerging technology has a cost limitation that is much lower than that for a mobile SoC. With a 3D-IC, however, a designer could achieve IoT capability without crowding everything into one single SoC.
Wang said 3D-ICs allow designers to:
- "De-risk" SoC implementation
- Reuse silicon-proven analog/mixed-signal dies
- Port digital logic to advanced nodes only
- Reduce power
- Improve signal integrity/power integrity vs. discrete packages and packages of packages (POP)
- Improve yield for larger die at advanced nodes
- Reduce form factor
- Have more security versus a supply chain attack (one die can be encrypted)
"Thermal is always the top issue from a design perspective," Wang said. He said the thermal performance of 3D-ICs is also a transient timing issue. Today POP thermal performance is better than that of Wide I/O (a memory standard for stacked die), he said. TSV requires silicon dies to be reduced to 50-70 microns, which results in poor lateral heat distribution. Thermally coupled Wide I/O DRAM heats up much faster than POP memory (0.08 seconds for Wide I/O versus 4 seconds for POP).
Wang spoke briefly of challenges in 3D design for test (DFT). Here again, the issue is really one of architecture re-design, and what's needed is new 3D-IC architectures that enhance memory redundancy repair and provide yield-focused digital design.
Yet another challenge is cost. 3D-ICs are currently not cost effective, Wang said. TSV is still an expensive process, a silicon interposer is an additional cost, and wafer thinning has a yield impact. Eventually, there will be an overall system-level cost advantage for 3D-ICs, but for now 3D-ICs are driven by performance, power, and form factor.
Design and Implementation Flows
3D-IC mandates a lot of changes in EDA methodology. Wang said that new features include package/silicon co-design, a new layout layer (back-side redistribution layer or RDL), new extraction features (such as TSVs), inter-process DRC/LVS, cross-die power and signal integrity, cross-die timing closure, thermal analysis, and test.
In the Cadence 3D-IC design methodology, a high-level extraction tool, Sigrity XCitePI Extraction, drives the co-design flow. It provides a distributed model extraction of full-chip power distribution network (PDN) and I/O nets. Following die/interposer/package co-design, users define a test architecture and do a detailed logic implementation that includes micro-bump placement and TSV array generation. Finally, designers can use timing-driven routing to compete the routing of the interposer. The following diagram from Wang's presentation offers a simplified view of this methodology.
Wang also showed an analysis and signoff flow (below). To provide high capacity signoff-quality extraction, it uses the recently announced Cadence Quantus QRC Extraction Solution. Inter-die checks are part of ERC (electrical rule checking). To run a thermal analysis, designers obtain a detailed power map from the Cadence Voltus IC Power Integrity Solution. Thermal analysis is provided by Sigrity PowerDC, which can provide a temperature map for each die.
Both the Cadence Encounter Digital Implementation System and the Virtuoso custom/analog platform have dedicated 3D-IC functions that work together. Cadence Allegro Silicon-in-Package (SiP) tools support end-to-end implementation, including early-stage implementation. Finally, Wang noted that Cadence has been working with ecosystem partners since 2007 on 3D-IC, and has completed eight test chips and one production chip.
John Ferguson and Dusan Petranovic—Rethinking Physical Verification
Ferguson said that today's physical verification tools are "not up to the challenge" of 3D-ICs. Chips are already "3D" in the sense that they have layers, but those layers are controlled by naming conventions and dedicated in specific ways by foundries. The tools assume that all polygons on a single layer are "co-planar" and can be merged. A 3D-IC that comes into this environment "will break everything," Ferguson said.
Thus, he said, physical verification tools must understand that geometries from one die placement may be different from other geometries that are potentially on the same layer. From a user point of view, he said, it's not difficult. Just run DRC and LVS on individual dies as always, and then tell the tool what the 3D assembly looks like. The tool will run the necessary checks and report the results. With 3D-ICs, there are DRC checks such as geometric overlap, LVS checks such as mismatch connections between source and layout, and location checks such as missing die-to-die physical connections.
Petranovic talked about three TSV modeling approaches. These include standalone TSV models, which are provided by foundries; they are easy to integrate into a flow, but not adequate for high-density, high-frequency designs. Compact parameterized models can account for some interactions between TSVs and are faster than a field solver. Finally, field-solver based TSV extraction is the most accurate, but also poses challenges in performance and integration.
Bill Martin—It All Starts Here
Martin is vice president of engineering at E-System Design, a startup that spun out of Georgia Tech's Packaging Research Center. One of the company's products is Sphinx 3DPF, a 3D-IC "pathfinder." It claims to offer fast, accurate, and unrestricted exploration at the very first stages of the design flow.
Pathfinding, Martin said, makes it possible to explore a number of implementations and pick one that is most likely to work. This can be done without wasting a lot of time and resources in implementation. Pathfinding can help designers with the most basic decisions—3D or 2.5D? Silicon or glass? What are the process parameters, topologies, configurations?
Martin provided many examples of discoveries by the Sphinx pathfinder, including some that are counterintuitive. For example, wire bonding can provide better performance than on-die TSVs up to 8GHz. A 50µm ball may improve insertion loss by 0.5dB, but it's not going to solve a larger design problem. In one example, a TSV plus RDL insertion loss was 14X worse than RDL alone.
As Martin said, "14X worse may be fine for your design. But you might want to understand it before you implement it."
Again, the presentations from the Working Group session are available here.
Richard Goering
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