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IoT Focus: Natural User Interface Design Crucial to Success
(Seow Yin Lim is the Group Director of Marketing for Cadence's IP Group and is responsible for driving Cadence's Internet of Things (IoT) strategy. Lim, who has worked at leading SoC companies, will...
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Advanced Profiling for SystemVerilog, UVM, RTL, GLS, and More
The profiler helps to figure out the components or the code streams that take the maximum time or memory during simulation. Over the years, profiling was more inclined toward RTL and GLS than...
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DDR4 Power-Aware Signal Integrity Adopting Serial Link Simulation Techniques
The signal integrity (SI) prophets had predicted this time would come, and it turns out they were right. The techniques that SI engineers have been using for the past decade to analyze multi-gigabit...
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3D-IC Working Group—Tool Support Needed, But “Gaps” May Be Narrowing
Where are the gaps in 3D-IC design, and how can they best be bridged? In order to provide a cost-effective alternative to silicon process scaling, work is still needed in 3D-IC design tools and...
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Highlights from Recent IEEE 802.3 Ethernet Standards Meeting
I wanted to share with you a number of updates from last month's IEEE 802.3 meeting in San Diego, California. Cadence has a comprehensive portfolio of design and verification IP, many of which support...
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New Technical Resources for Encounter Test Users on http://support.cadence.com
Hello Encounter Test Users, In this blog, I would like to introduce a few knowledge artifacts that will provide an easy way for you to learn about and stay productive with this product, technology, and...
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Whiteboard Wednesdays - Verification Made Easy with Memory Models
In this week's Whiteboard Wednesdays, Tom Hackett explains memory models and their role in verifying memory interfaces in today's SoCs. He'll explain the differences betweeen memory models and...
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Flash Memory Summit: Marveling at IBM’s Staying Power
SANTA CLARA, Calif.—Sometimes in this mile-a-minute business of ours, you have to sit back and reflect. Today, I'm thinking about 103-year-old IBM.Most technology companies have a relatively short...
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IBM Lithography Expert: Making 10nm IC Design Possible
Development work is underway on the 10nm process node - but can we get there with conventional lithography? In a recorded presentation available at the Cadence web site, Lars Liebmann, distinguished...
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Whiteboard Wednesdays - USB Controller Connectivity
In this week's Whiteboard Wednesdays, Jacek Duda continues his discussion about USB controllers. This time, the conversation focuses on High-Speed Interchip Connectivity (HSIC) and Super Speed...
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What's Good About Allegro Design Workbench Team Collaboration? Find Out in...
The Allegro Design Workbench Team Design Option (TDO) offers two (2) specific integrator roles for team design and collaboration:Logical design integrator Responsible for front-end designPhysical...
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Create Ideal Solder Mask Openings Around Bond Fingers with Cadence 16.6 IC...
Normal 0 false false false EN-US X-NONE X-NONEExposing metal through solder mask openings is as necessary as it can be frustrating. For regular arrays and grids of pins of a flip chip, embedding the...
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IoT Focus: Wrestling with the Design, Time to Market, and Cost Challenges of IoT
You know we live in astonishing times when you can start your car by talking into your phone. But the era of the Internet of Everything--for all the great technology it has begun to enable--is filled...
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Electromigration – What IC Designers Need to Know
If a chip that was previously working fails in the field, the impact could range from a minor nuisance (for a disposable consumer product) to a major tragedy (for a pacemaker or automobile safety...
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Expectations Versus Reality — How I Misjudged the Apple MacBook Pro Retina...
In technology, simple concepts can have huge implications, and sometimes what you might dismiss as a minor feature, turns into a major improvement. For example, let me tell you about my experience...
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Virtuosity: 20 Things I Learned in July and August 2014 by Browsing Cadence...
Apologies for skipping a month, but things got a bit hectic, so enjoy a double-dose of browsing today.Application Notes1. Cadence Online Support Release HighlightsNew features for searching and...
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Objection Mechanism Synchronization Between SystemVerilog and e Active...
Suppose you have two verification components, each driving its own portion of the DUT (for example, two protocols driving a DUT, one implemented in e and the other in System Verilog).In this case, you...
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Whiteboard Wednesdays—How to Verify SoCs Incorporating the M-PCIe Specification
In this week's Whiteboard Wednesdays video, Mukul Dawar provides an overview of the Mobile PCIe (M-PCIe™) specification. He explains how Cadence VIP for M-PCIe can help you verify your mobile SoC design.
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Customer Support Recommended – Using Test {oints in Allegro Design Entry CIS...
A test point is a location within an electronic circuit that is used to either monitor the state of the circuitry or to inject test signals. Test points have two primary uses:During manufacturing they...
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Apple Announcement’s Implications for Systems Design
Next week, Apple is holding a press event (Sept. 9), when, rumor has it, the company will unveil a new smartphone and a wearable electronic device (perhaps a smart watch).These are more than just...
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