If a chip that was previously working fails in the field, the impact could range from a minor nuisance (for a disposable consumer product) to a major tragedy (for a pacemaker or automobile safety system). That's why reliability is so important in IC design, and more specifically, why electromigration has become a major concern at 28nm and below.
Electromigration (EM) refers to the unwanted movement of materials in a semiconductor. If the current density is high enough, there can be a momentum transfer from moving electrons to the metal ions that make up the lattice of the interconnect material. The ions will drift in the direction of the electron flow. The result is the gradual displacement of metal atoms in a semiconductor, potentially causing open and short circuits.
While EM has been a problem since 90nm or even earlier, it gets worse at advanced nodes such as 20nm and below. That's because wires are thinner and current densities are higher. As you scale the wires down to more advanced process nodes, resistance increases and more current is needed. Similarly, to get the performance you need from devices, you may need to increase the current density.
At advanced nodes, said Vassilios Gerousis, distinguished engineer at Cadence, "EM becomes a new component that you have to optimize. Besides timing and power, you now have to deal with EM." At 28nm, he said, you can probably "count on your fingers" the number of nets that pose EM violations. At 16nm it might be 500 or 1,000 nets if you do up-front prevention - or perhaps 10,000 if you don't.
Why It Matters
So, what can go wrong when metal atoms drift away from their intended positions? One problem is open circuits due to voids in wires or vias. Another problem is short circuits due to extrusions or "hillocks" on wires. Either can cause a system failure that is hard to diagnose.
Here are some other points about EM that emerged from my conversation with Gerousis:
- At older process nodes people worried mostly about EM on power wires and clock wires. But now signal wires need to be considered as well. Therefore, both DC (power) and AC (signal) EM are problematic.
- FinFETs have more current density than planar transistors, and thus make EM worse, especially in conjunction with narrow wires.
- Copper interconnects worsen EM because the copper molecule moves faster.
- The lower supply voltages you get with scaling help reduce EM, but not enough to offset all the other causes that amplify it.
- EM is worse at higher temperatures.
- EM mitigation techniques, such as widening wires, can not only increase area - they can cause timing violations. EM fixing needs to be timing-driven.
Fortunately, there are well-known ways to reduce current density and mitigate electromigration. Unfortunately, they all have area or performance tradeoffs. They are:
- Widen the wire to reduce current density
- Reduce the frequency
- Lower the supply voltage
- Keep the wire length short
- Reduce buffer size in clock lines
To control EM, foundries define current limits for each wire. Gerousis noted that a lot goes into this calculation, including wire width, layer, activity, frequency, and temperature. The width and length of the wires then becomes part of the design rule set. But it's not a simple matter of just following the rules. "If you increase the width you change the spacing," Gerousis noted. "You need to take care of not just the width, but also the spacing of neighboring wires."
Analyzing EM
To prevent EM failures in the field, you need an effective EM analysis solution that can show you how to mitigate EM without sacrificing too much area and performance. Basically, an EM analysis solution calculates the current on each wire and compares it to foundry EM rules. It then ideally links to an IC implementation toolset for automated or manually assisted fixing.
Here's a snapshot of how Cadence tools handle EM analysis:
- The Quantus QRC Extraction Solution performs an "EM aware" RC extraction on the layout. QRC understands the layout rules for EM.
- For custom/analog designers, the Voltus-Fi Custom Power Integrity Solution provides transistor-level EM and IR drop analysis. It runs with the Cadence Spectre-APS simulator, which solves the matrix for the RC power network for transistor-level accuracy. The Voltus-Fi tool then runs EM and IR drop checking and back-annotates layouts to the Cadence Virtuoso custom/analog platform for analysis and fixing.
- For digital designers, the Voltus IC Power Integrity Solution provides full-chip EM analysis along with other types of power analysis. The Voltus tool works with the Cadence Encounter Digital Implementation System for automated fixing.
As shown below, the Voltus-Fi tool generates a "power grid view" (PGV) after the EM and IR drop checks are completed. This is a macromodel that includes physical layout information and also captures electrical information. It can be passed to the full-chip Voltus power analysis tool for use in SoC signoff power analysis.
Even with these post-layout analysis capabilities, Gerousis noted, Cadence advises that designers do some EM prevention up front. And even with that, he said, "you will have some violations. That's why we have a fixing strategy."
Automated tools are helpful, but EM is not totally transparent to digital designers. They still need to understand the problem, use prevention (such as wider wires or smaller buffers on clock trees), run an EM analysis, and fix violations. "In addition to power, timing and leakage, electromigration is another factor people have to worry about," Gerousis said. A little knowledge and a good set of tools can help you worry a lot less.
Richard Goering
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