Apologies for skipping a month, but things got a bit hectic, so enjoy a double-dose of browsing today.
Application Notes
1. Cadence Online Support Release Highlights
New features for searching and filtering, viewing cases and providing feedback
2. Generic Process Design Kit Downloads
Get the latest versions of the Cadence Generic Process Design Kits (GPDK) and standard cell reference libraries, which are provided for use with Cadence Design Tools and Flows of Virtuoso and Encounter products. They are intended to be representative of actual semiconductor process.
3. Exchanging OA Database Views between Encounter (EDI) and Virtuoso (IC)
Talks about the basic things to know when interoperating between Encounter and Virtuoso for doing Analog-on-Top or Digital-on-Top design.
4. AMS Supply-Sensitive Connect Modules Application Note
Supply-sensitive connect modules offer a way to cleanly and accurately handle analog-to-digital and digital-to-analog conversion in analog/mixed-signal circuits involving multiple supplies and multiple voltages (MSMV). This document provides multiple examples of how to implement this functionality.
Compact presentation of the mostly frequently asked questions (and answers) to customer support regarding licensing.
How to set up Cadence licensing using USB dongles.
7. Layout Enhancements in IC6.1.6 ISR7 and ICADV12.1 ISR9
Describes new layout functionalities in the areas of Creating/Editing, Object Selection cycling, Copy/Move mirroring, Via Generation, Cloning, virtual connection and hierarchical extraction from selected instances.
8. Creating Batch Triggers in PVS
How to set up pre- and post- triggers from the Virtuoso GUI environment to perform various tasks before or after a PVS run.
Videos
9. Creating Pad Ring using Power Router
This video demonstrates how to create Pad routes using Power routing GUI in Virtuoso and save routing schemes for future use. It also shows SKILL rtePowerRoutePadRing command that can be used instead of GUI approach.
10. Introduction to Customer Support
Lots of great information about how to be more effective in using http://support.cadence.com. Plus male AND female computer voices.
Covers how to update Modgen constraints after device or constraint parameters have been updated in the schematic, and how to update the constraint view with Modgen changes made in the layout view.
12. New Features in SimVision 14.1 Release
Covers Driver tracing enhancements, Schematic Tracer, UVM and RTL Debug and other ease-of-use enhancements.
Rapid Adoption Kits
Detailed workshop demonstrating different methods of characterizing PLL's and their principal components.
14. Using VEC and VCD Files in AMS and Analog Simulation in ADE
Explains (and walks through) how to use digital stimulus (VCD, EVCD and VEC) files in AMS simulation with Spectre/Ultrasim as the analog solver.
Demonstrates features of ADE XL and ADE GXL to perform Monte Carlo analysis, create fast K-sigma statistical corners and use circuit optimization to tune design performance and improve circuit yield.
Basics of using the Virtuoso Layout Suite, updated for IC6.1.6 ISR6.
17. Electrically Aware Design (EAD) Worskhop
EAD allows extraction of layout parasitics at any arbitrary point in a design cycle, including parasitic resimulation and electromigration analysis. Updated for IC6.1.6 ISR7.
Blogs
18. Voltus-Fi Custom Power Integrity Solution: Electromigration and IR Drop at the Transistor Level
Introduces Cadence's new tool which provides transistor-level electromigration and voltage drop analysis with foundry-certified SPICE accuracy.
19. Quantus QRC Extraction Solution -- Massive Parallelism Extracts Accurate Parasitics Quickly
Introduces Cadence's release of a next-generation parasitic extraction tool that leverages massive parallelism to deliver up to 5X faster turnaround time.
20. EDA Plus Academia: A Perfect Game, Set and Match
Well-deserved kudos for collaborative research between Carnegie Mellon University and Cadence on a radically new statistical analysis methodology which won the newly established Best Poster Award a the ACM SIGDA Ph.D. Forum at this year's DAC.
Stacy Whiteman