Think it is easy to design and verify a wireless, connected, ultra-low power, dirt cheap device with analog, digital, and sensor technology? It’s a complicated task that requires an ecosystem with process technology, tools, and IP, according to panelists at the recent Mixed-Signal Technology Summit convened by Cadence Oct. 28, 2014. The panel was titled “ Ecosystem and Design Enablement for IoT ,” and the discussion went far beyond the challenges of integrating analog and digital design. In particular, panelists talked a great deal about power management and the use of such techniques as power islands and dynamic frequency and voltage scaling (DVFS). They also discussed the difficulty of analog/mixed-signal verification, especially in the presence of low-power design techniques. The panel was moderated by Brian Fuller , editor-in-chief at Cadence. Panelists were as follows, shown from left to right in the photo below: Douglas Pattullo , technical director, TSMC Advanced Technology Group Ron Moore , vice president of marketing, ARM Physical Design Group Ian Dennison , solutions senior group director, Custom IC and PCB Group, Cadence Rob Cosaro , chief architect, Freescale Silicon Valley Design Center Panelists were first asked to briefly present their views on mixed-signal enablement in the ecosystem. Here are some responses. Cosaro – The most important thing is that digital and analog teams work together. Tools are important, but it’s more important to understand the requirements and the specs and work together as a team. I can give you all kinds of stories about what happens when people don’t talk. Bad things have happened just because people renamed things. Dennison – We’ll have a lot of edge nodes in the office, factory, energy management, hospitals, retail, farming, security, buildings, cities, cars, ships, wearable, transport – when we populate the world with these things, it’s going to generate a lot of traffic. And that can only be good for business in the fog (the layer between the cloud and the ground) and in the cloud itself. However, not all edge nodes will be dumb devices that rely on the compute power of the cloud to do all the analytics. With all this traffic flying around, some edge nodes simply won’t be able to afford the latency. We will have a diversity of applications, a diversity of sensing requirements and a diversity of performance requirements, which all add up to a lot of silicon and a lot of design. Moore – You have to have really low leakage and optimized power management for always-on blocks. You have to have very good noise immunity and integration of digital with analog. And it’s got to be very, very low cost, because you’re going to deploy millions of these, ranging from 25 cents to up to $5 per unit. There are a lot of challenges ahead for us to do that. Pattullo – Everyone looks at IoT as a wave of innovation to come. I contend it is here already. For some customers at least 10 percent of their current TSMC silicon is going into these applications. Of course, low power is needed but it’s not just a single technology. We support everything from 0.18 [microns], which probably accounts for most of today’s IoT devices, to 16nm FinFET, which is a great low-power technology that has a lot of advantages. Q: What has been the most important upgrade to your mixed-signal methodology in the past five years? Cosaro – Low power is a really important topic for IoT. Eight years ago I started working on the idea of turning [voltage] islands off and on. It sounds simple, but when we got a chip back it did not work. Now we can tape out chips and have relatively few issues. I think the idea of having isolation-aware tools and being able to insert level shifters is a big deal. Going forward, I think noise will be an even bigger issue. Moore – We’re trying to shrink the footprint of the standard cells that are used to implement digital blocks. We’re trying to get low power and low leakage. We’re using a lot of thick gate-oxide type cells in order to have low leakage areas, and we’re coming out with what I would call near threshold logic. Dennison – Low power is extremely important for IoT. We need low-power IP and ultra-low-power processors. We need low-power methodologies and solutions. Multiple supply voltages are a great way to reduce leakage and dynamic power dissipation. We need tools that support DVFS so you can step down the energy of your block. If you have multiple voltage threshold support from libraries in your process, your synthesis tools can minimize the leakage. Q: What about mixing in MEMS and the physical characteristics of modeling and verification? Dennison – Cadence has a MEMS partner, Coventor. If a mechanical engineer is designing a MEMS device, Coventor products will produce an s-parameter model that can be used in SPICE simulation. Virtuoso ADE-XL can optimize MEMS and analog parameters together. (Note: a previous blog post has more information about the Coventor/Cadence link). Q: Do you see significant changes in technology roadmaps because of how we will need to design for IoT going forward? Cosaro – Really it’s all about wireless connectivity. There is a strong push by customers who want MEMS, MCU, and wireless all on one device. They think that’s cheaper, but it’s not necessarily so. Right now the processes don’t fit well together. The libraries are not there, the kits are not there. Moore – TSMC Open Innovation Platform has over 130 partners, 39 IP providers, and 30 or so EDA vendors. Getting kits together is an ecosystem problem. That’s why ARM is invested in working with TSMC and Cadence. We want to make sure we’re optimizing our IP with the processes and methodologies along the way. Pattullo – TSMC has always been in the business of helping customers move to the next node. However, for some products, 28nm may be the last time this migration happens. When you move below 22nm it gets expensive. Many big customers will move to 16nm, but for some applications, companies will start moving back to larger geometries. We’ll see more activity at 40nm, 65nm, and even 0.18 microns. A lot of re-engineering is going into these processes using what we’ve learned from advanced nodes. Q: We’ve talked about the design challenges of IoT. What kind of verification problems do you see? Cosaro – My big concern about verification is whether everything works well in different environments. For example, we have a radio on chip and we want a DC converter so we can connect directly to the batteries. The radio works fine by itself but when you turn the DC converter off, it no longer works. Another problem is startup issues – does everything turn on correctly? Have I figured out all the isolation problems? Dennison – I think verification problems in the cloud are getting worse. For edge nodes everybody is talking about more GHz, more bandwidth. With verification, you worry not only about the integration of sensors and RF and processors, but doing it with low power. Cosaro – To verify power, you have to have the spec up front of what you expect the part to do. If you don’t do that you are just going to get what you get. Look at where you are before you tape out. In the past few years of my experience, that’s been really successful. Richard Goering Related Blog Posts Q&A: MEMS Begin to Enter the Semiconductor Design Mainstream IoT Focus: IoT Applications Require a New Architectural Vision Linley Conference: The Processor Dilemma for IoT and Mobile![]()
![]()
↧