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Blog Post: Q&A: Kaufman Award Winner Lucio Lanza Helps Launch Innovative EDA...
Lucio Lanza, managing director of Lanza techVentures LLC, has been selected by the EDA Consortium (EDAC) and the IEEE Council on EDA (CEDA) to receive the EDA industry’s highest honor – the 2014 Phil...
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Blog Post: Call for Papers Now Open – CDNLive Silicon Valley
CDNLive Silicon Valley (March 10-11, 2015, Santa Clara Convention Center) provides an excellent opportunity to share your experiences and insights on key technical and industry issues. And it’s not...
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Blog Post: It’s Late, But the Party is Just Getting Started
With some important public events now behind us and more on the horizon, the agendas make it clear that there is mounting pain in the realm of verifying chips with a significant blend of analog and...
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Blog Post: Generic dynamic run-time operations with e reflection Part II
Field access and method invocations In the previous blog , we explained what are untyped variables and value holders in e , and how to assign and retrieve values to/from them. In this and the next...
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Blog Post: Functional Safety and ISO 26262: Designing Against the Worst Case
DETROIT--Functional safety requirements in automotive electronics design--in the context of ISO 26262--boil down to this: teams not only need to avoid the nightmare failure scenario, they need to get...
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Blog Post: Linley Conference: The Processor Dilemma for IoT and Mobile
Data processing presents difficult choices for designers of Internet of Things (IoT) and mobile devices. If you’re designing a device that must have low power, a small form factor, and an inexpensive...
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Blog Post: Transferring e "when" Subtypes to UVM SV via TLM Ports—UVM-ML OA...
The UVM-ML OA (Universal Verification Methodology - Multi-Language - Open Architecture) package features the ability to transfer objects from one verification framework to another via multi-language...
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Blog Post: Its Name is C, Type-C: The New Superhero of Cables from USB
Isn’t it interesting how, with time, all the nitty-gritty of technology is starting to get more and more attention? Is it because we’re getting smarter, or is it that everything is so much the same on...
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Blog Post: Where Is the Money for IoT?
I attended the Gartner Semiconductor briefing on Oct. 23, 2014, the theme of which was “The Internet of Things: Use Cases that Move Beyond the Hype.” Most attendees were from the semiconductor...
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Blog Post: Using Virtuoso Custom Design Platform to Model an Engine Control Unit
DETROIT—In automotive electronics applications, the environment around a typical engine control unit is unforgiving. It’s unforgiving environmentally, and there’s no room for failure because safety is...
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Blog Post: Whiteboard Wednesdays—Verification IP Productivity Tools
In this week's Whiteboard Wednesdays video, Tom Hackett talks about Cadence Verification IP (VIP) productivity tools in the VIP catalog. These tools, PureView and TripleCheck, help engineers better...
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Comment on Its Name is C, Type-C: The New Superhero of Cables from USB
Well, let's see what Apple has to say about this connector, because in general the marketing department at Apple has been giddy to keep their connectors non-standard so that they can maximize revenues...
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Blog Post: Mixed-Signal Summit Panel: Why IoT Design is Harder Than it Looks
Think it is easy to design and verify a wireless, connected, ultra-low power, dirt cheap device with analog, digital, and sensor technology? It’s a complicated task that requires an ecosystem with...
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Blog Post: The Elephant in the Room: Mixed-Signal Models
Key Findings: Nearly 100% of SoCs are mixed-signal to some extent. Every one of these could benefit from the use of a metrics-driven unified verification methodology for mixed-signal (MD-UVM-MS), but...
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Blog Post: Webinar: Insights into Extraction, Timing, and Power Signoff at 16nm
As the 16nm FinFET node ramps, the potential for engineering productivity gains and design creativity abound, but so too do the challenges. Engineers from Cadence and TSMC recently laid out many of the...
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Blog Post: Do You Design Wafer-Level Chip-Scale Packages? Cadence 16.6 SiP...
As these types of designs see an increasing number of applications and design starts, we need tools that make it as easy and efficient as possible to turn them from a specification to a finished...
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Blog Post: Mixed-Signal Keynote: Will We Return to Analog Signal Processing?
Sometimes old ideas become new again. That may be the case with analog signal processing, which is far more efficient than digital signal processing in some applications, according to Boris Murmann,...
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Blog Post: Q&A: Sigrity's An-Yu Kuo on Chip-Board-Package Design...
In July 2012 Cadence announced its acquisition of Sigrity , a leading provider of signal integrity (SI) and power integrity (PI) analysis tools. Jiayuan Fang, Sigrity founder, led the team for the...
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