The Cadence Tensilica team traveled to Tel Aviv to host a special processor-technology focused track at CDNLive Israel (Nov. 3). It’s a region long known for IP, DSP, and SoC startup development as well as having significant design centers from the likes of Intel, Qualcomm, Marvell, Freescale, and many other silicon vendors. The three-and-a-half hour session featured talks by Cadence and three partners/customers of the Tensilica data-plane processor technology of Cadence. Chris Rowen , CTO of the IP Group of Cadence, teed it up by describing the technologies and methods of data-rich application optimization using Tensilica’s LX6 processor generator. In his talk titled “Xtensa Dataplane Processor Technology: The Innovation Platform for Data-Rich Silicon Applications in the Connected Universe,” Rowen highlighted the growing necessity of processor configurability to achieve the throughput, energy efficiency, and I/O structures needed to achieve SoC and software goals. Rowen also updated the audience on Tensilica application-domain processor families for audio, voice, baseband DSP, imaging, and vision processing. The theme of application diversity in this talk was amply reinforced by the customer application talks that followed. View from the Designers Albert Yosher , Principal Engineer for Qualcomm Israel, gave a talk titled “High performance at low power baseband SoC for wireless base station.” Yosher discussed the need to increase mobile capacity by 1000X, made possible by a combination of higher spectral efficiency in algorithms, more available spectrum, and proliferation of more and smaller cells. The DAN3K platform from Qualcomm aims at high parallelism at modest clock-rate, with a combination of dedicated functions and rich DSP programming from High Level Language (HLL) to enable rich flexibility and easy enhancement. The DSP architecture includes more than 300 instructions optimized for LTE data processing, with three-way VLIW processing and 128-bit wide SIMD data-path, all clocked at 600MHz in a 40nm process. The processor’s HLL environment includes automatic software pipelining, and loop unrolling, and register allocation. Yosher noted that instruction scheduling was “near to perfect” and it was never necessary to write assembly code because the compiler could do scheduling better. The development environment included clock-accurate simulation, pipeline visualization in the GUI and integrated source-level debugging, even including customer register views. The architecture also uses tightly coupled memories for performance-critical tasks, supported with multi-ported on-chip memories and multiple off-chip DDR interfaces Eli Ariel , satellite navigation expert and founder of Galileo (GSN), gave the talk, “GSN Software Programmable GNSS Receiver.” GSN is a leading provider of GPS receivers, simulators and indoor navigation solutions. Ariel described the fundamentals of GNSS receivers, especially the acquisition and tracking phases of finding and decoding satellite signals, and the navigation computation, which triangulates position based on known trajectories to produce exact x,y, z position, velocity, and time. GSN offers a pure Software-Defined Radio solution using Tensilica BBE16 BaseBand Engine DSPs. Ariel outlined the technology’s high-bandwidth architecture, highlighting the advantages in both reduced hardware complexity and software programmability, especially to adapt to new scenarios, constellations, RF units, and host interfaces. Power Optimization The talk also contrasted the typical GPS tracking power dissipation in current smartphones; typical is several hundred mW, while the total power dissipation of the software-defined radio implementation of GNS is less than 20mW, he said. Next, Ariel demonstrated GNSS performance using GNS’s GENOS simulator, including driving through a complex urban environment. He finished by detailing the modest MHz, instruction memory, on-chip data memory, and off-chip memory requirements of the GNS system. Shlomo Peller of Rubidium gave a talk titled “Get Your Head Out of the Cloud—Always-on, Very Low Power Embedded Speech Recognition.” Rubidium is a leading provider of test-to-speech, speech recognition, speech compression, and biometric speaker identification. Rubidium supports voice recognition on the Tensilica HiFi audio DSP family. Click here for additional CDNLive Israel materials and resources. Brian Fuller Related stories: - CDNLive 2014: Follow the Data to Optimize System Design--Chris Rowen - Call for Papers Now Open—CDNLive Silicon Valley![]()
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