Clik here to view.
Blog Post: Virtuosity: A Very Large Number of Things I Learned in September...
There has been a flurry of activity on COS over that past couple of months. I can't even come close to listing everything, but here are some of the highlights. Be sure to check out the "Training Bytes"...
View ArticleClik here to view.
Blog Post: Designing Automotive Ethernet Using Allegro, Sigrity Tools
DETROIT—As automotive engineering teams embrace more electronics in their systems, the need to design, analyze, and simulate those systems at a higher level has become imperative. This is not just a...
View ArticleClik here to view.
Blog Post: Multi-Fabric Planning for Efficient PCB Design
Recently, an article was published in Printed Circuit Design and Fab about Multi-Fabric Planning for Efficient PCB Design (see page 22 of printed magazine). Today's BGA-style packages have a...
View ArticleClik here to view.
Blog Post: The Power of Big Iron
Key findings: 5X to 32X faster low-power verification using Palladium XP emulation It’s hot in July in Korea, and not just the temperature; the ideas, too. The ideas that flowed at CDNLive Korea were...
View ArticleClik here to view.
Blog Post: JUG Keynote—How Jasper Formal Verification Technology Fits into...
Jasper Design Automation had leading-edge formal verification technology before its acquisition by Cadence this summer. A picture of how this technology fits into the Cadence system verification flow...
View ArticleClik here to view.
Blog Post: Whiteboard Wednesdays—TripleCheck VIP
In this week's Whiteboard Wednesdays video, Moshik Ruben discusses TripleCheck verification IP (VIP) and how it allows engineers to know they have a thoroughly tested design that complies with the...
View ArticleClik here to view.
Blog Post: Automotive Ethernet Growth to Accelerate Once Headwinds Pass: Analyst
DETROIT—The direction of travel for automotive Ethernet applications is clear: up and to the right. But the growth of the technology’s adoption faces stiff headwinds in large part due to the automotive...
View ArticleClik here to view.
Blog Post: JUG Keynote: Formal Verification’s Evolving Democratization and Scale
SANTA CLARA, Calif.—When commercial formal verification tools started to take flight a couple of decades ago, a common quip was that the technology was “built by PhDs for PhDs.” That the technology had...
View ArticleClik here to view.
Blog Post: Q&A: Moving Towards Use Case and Software-Driven Verification
Existing verification automation techniques – such as metric-driven verification, constrained-random test generation, and the Universal Verification Methodology (UVM) – have greatly eased block-level...
View ArticleClik here to view.
Blog Post: What's Good About Allegro PCB Editor Select by Lasso or Path? 16.6...
The 16.6 Allegro PCB Editor release contains two new selection options, lasso and path, which are available with commands that normally support temp groups; ‘Move’ and ‘Highlight’ are two examples of...
View ArticleClik here to view.
Blog Post: Whiteboard Wednesdays—SoC Interconnect Verification
In this week's Whiteboard Wednesdays video, Tom Hackett discusses the VIP Catalog solution for SoC Interconnect Verification. Two products are provided: the Interconnect Validator, which monitors...
View ArticleClik here to view.
Blog Post: Mixing It Up in Hardware (an Advantest Case Study in Faster...
Trolling through the CDNLive archives, I discovered another gem. At the May 2013 CDNLive in Munich, Thomas Henkel and Henriette Ossoinig of Advantest presented a paper titled “Timing-accurate emulation...
View ArticleClik here to view.
Blog Post: Business Outlook “Better Than Fine,” Economist Goolsbee Says
A man once crowned the funniest celebrity in DC stood before the semiconductor industry’s leading lights to say that if we think we think the economy is going to turn around any time soon we’re...
View ArticleClik here to view.
Blog Post: Whiteboard Wednesdays—Selecting the Right DDR PHY Solution
In this week's Whiteboard Wednesdays video, Kishore Kasamsetty reviews evaluation criteria when purchasing a DDR PHY IP solution. Kishore details topics such as power, performance, and area (PPA),...
View ArticleClik here to view.
Clik here to view.
Blog Post: JUG 2014: Cadence Unveils Ambitious Roadmap for Formal Verification
The Cadence acquisition of Jasper Design Automation this summer made Cadence the overnight leader in the formal verification market. Today the Formal and Automated Verification (FAV) group at Cadence...
View ArticleClik here to view.
Blog Post: Panel: Engineers Debate Progress of Low-Power Design
Low-power design for electronic systems has made significant progress, but there are still disconnects at the software and architectural levels, according to panelists at the Low-Power Technology...
View ArticleClik here to view.
Blog Post: Leveraging Cadence IP for Automotive Audio
DETROIT—Derek McAulay is one hardy Scotsman. The Cadence principal design engineer had just landed from his trans-Atlantic flight when he dived right into a technology demo here at the IEEE Standards...
View ArticleClik here to view.
Blog Post: CDNLive Israel: Optimizing SoC Design in Data-Rich Applications
The Cadence Tensilica team traveled to Tel Aviv to host a special processor-technology focused track at CDNLive Israel (Nov. 3). It’s a region long known for IP, DSP, and SoC startup development as...
View ArticleClik here to view.
Blog Post: Code Coverage at the System Level with Hardware-Assisted...
Short answer: Nope, not kidding. You can get value from applying code coverage with hardware-assisted verification by focusing on actionable data. Longer answer, keep reading below to learn more....
View Article