Front-end design has been at the heart of EDA for decades, but it is not a “solved problem.” Today massive complexity is challenging such tasks as RTL design creation, synthesis, design for test, ECO handling, and static low-power verification. You can learn about the latest technologies in these areas at the Front-End Design Summit at Cadence San Jose headquarters Thursday, Dec. 11, 2014. The Front-End Design Summit is a free, one-day conference. It begins with a keynote speech by Paul Cunningham, Vice President of R&D for Front-End Design at Cadence, titled “ Innovations in Synthesis, Formal Verification, and Test. ” As shown on the schedule below, the conference also includes presentations from Cadence customers at Freescale, Broadcom, Cisco, Atmel, PMC-Sierra, and Soft Machines. Phil Bishop, Vice President of R&D for High-Level Synthesis at Cadence, will give a presentation titled “ Adopting Physical Synthesis Techniques for a More Convergent HLS Flow .” Finally, the summit concludes with a panel discussion titled “ Runtime and Results: Optimizing Your Front-End Design Flows in an Era of Mounting Complexity. ” It will include panelists from Applied Micro Circuits, Broadcom, Cadence, Cisco, and Qualcomm. Panelists will give their views on topics such as RTL design times, ECOs, physical synthesis, low-power design, and static verification. Here’s the schedule for the event. Space is limited, so please register . 9:00 am – Registration and breakfast 9:30 am – Welcome 9:35 am – Innovations in Synthesis, Formal Verification, and Test. Paul Cunningham, Vice President of R&D for Front-End Design, Cadence (Watch realtime highlights of this keynote here. ) 10:20 am – Do’s and Don’ts of Running Physical Synthesis. Ravi Vaidyanathan, Freescale 11:05 am – Tackling Challenging ECOs for Complex Networking SoCs. Vijay Adusumilli, Broadcom 11:35 am – Physical Multi-Bit Cell Inferencing for Complex Networking SoCs. Venkataraman Srinivasagam, Cisco 12:05 pm – Lunch with Cadence R&D 1:00 pm – Adopting Physical Synthesis Techniques for a More Convergent HLS Flow. Phil Bishop, Vice President of R&D for High-Level Synthesis, Cadence. 1:30 pm – Low-Power Static Verification Flow from RTL-to-Tapeout. Tai Le, Atmel 2:00 pm – Using Hierarchical Test Features to Increase Fault Accounting Accuracy. Jon Haldorson, PMC Sierra 2:45 pm – CPU Design Case Study: Using Physical Synthesis to Shrink the Floorplan. Te-Chen Tsai, Soft Machines 3:15 pm – Runtime and Results: Optimizing Your Front-End Design Flows in an Era of Mounting Complexity. Panelists from Applied Micro Circuits, Broadcom, Cadence, Cisco , and Qualcomm . 4:05 pm – Final Q&A, iPad drawing 4:20 pm – Networking event Richard Goering Related Blog Post – 2013 Front-End Design Summit Front-End Design Summit: The Future of RTL Synthesis and Design for Test![]()
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