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Blog Post: Whiteboard Wednesdays—Consumer DRAM Trends
In this week's Whiteboard Wednesdays video, Lou Ternullo explains the DRAM trends in today's consumer market. He deep dives into the comparison between LPDDR4 and DDR4 DRAM. (Please visit the site to...
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Blog Post: Front-End Design Summit Tackles Complexity
Front-end design has been at the heart of EDA for decades, but it is not a “solved problem.” Today massive complexity is challenging such tasks as RTL design creation, synthesis, design for test, ECO...
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Comment on Why Multi-Mode, Multi-Corner (MMMC) ECO Closure Requires a New...
WCC means.... Worst Case Cold Corner
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Comment on Why Multi-Mode, Multi-Corner (MMMC) ECO Closure Requires a New...
wcc means worst case cold corner
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Comment on Five-Minute Tutorial: Setting Up Clock Routing Rules
Hi Kari, can we use a modified shape/ tree as the clock tree in cadence? Which is the common clock tree used now?
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Blog Post: Five Reasons I'm Excited About Mixed-Signal Verification in 2015
Key Findings : Many more design teams will be reaching the mixed-signal methodology tipping point in 2015. That means you need to have a (verification) plan, and measure and execute against it. As 2014...
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Blog Post: Code Coverage at the System Level with Hardware-Assisted...
In yesterday’s Part I blog post , I talked about a technique for focusing code coverage efforts on actionable data—namely, focusing on higher level connectivity. Here, let’s discuss a second technique...
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Blog Post: How Sonics Uses Formal Verification for SoC Interconnect IP
As a leading provider of highly configurable network-on-chip (NoC) interconnect IP, Sonics Inc . faces a difficult verification challenge: A simulation-only approach takes too long to verify thousands...
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Comment on Five-Minute Tutorial: Setting Up Clock Routing Rules
hi Neeraja, I don't know that there is any "common" tree used. It's really design-dependent. As for other shapes, I'm guessing you mean things like H-tree, etc. I don't have any experience with those,...
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Blog Post: USB Power Delivery Is Better with Type-C
In my previous blog post , I wrote how much better than the existing Type-A and Type-B plugs the recently announced Type-C connector will be. Actually, the Type-C connector is only a part of the...
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Blog Post: Time to Play - You Can Now Run Your e Code on EDAplayground
Over the years I've often hoped to have the ability to show someone (a customer, or one of our field engineers) a bit of e code, and explain what it actually does. People say that a picture speaks more...
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Comment on Design Signoff Begins In Implementation
Hi does any body know about the double clock violation in cross talk..I know about glitch & incremental delay. I would like to know what exactly is this double clock violation
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Whiteboard Wednesdays—SoC Interconnect Verification
In this week's Whiteboard Wednesdays video, Tom Hackett discusses the VIP Catalog solution for SoC Interconnect Verification. Two products are provided: the Interconnect Validator, which monitors...
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Mixing It Up in Hardware (an Advantest Case Study in Faster Full-Chip...
Key Findings: Advantest, in mixed-signal SoC design, sees 50X speedup, 25 day test reduced to 12 hours, dramatic test coverage increase. Trolling through the CDNLive archives, I discovered another gem....
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Business Outlook “Better Than Fine,” Economist Goolsbee Says
A man once crowned the funniest celebrity in DC stood before the semiconductor industry’s leading lights to say that if we think we think the economy is going to turn around any time soon we’re...
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Whiteboard Wednesdays—Selecting the Right DDR PHY Solution
In this week's Whiteboard Wednesdays video, Kishore Kasamsetty reviews evaluation criteria when purchasing a DDR PHY IP solution. Kishore details topics such as power, performance, and area (PPA),...
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JUG 2014: Cadence Unveils Ambitious Roadmap for Formal Verification
The Cadence acquisition of Jasper Design Automation this summer made Cadence the overnight leader in the formal verification market. Today the Formal and Automated Verification (FAV) group at Cadence...
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Panel: Engineers Debate Progress of Low-Power Design
Low-power design for electronic systems has made significant progress, but there are still disconnects at the software and architectural levels, according to panelists at the Low-Power Technology...
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Leveraging Cadence IP for Automotive Audio
DETROIT—Derek McAulay is one hardy Scotsman. The Cadence principal design engineer had just landed from his trans-Atlantic flight when he dived right into a technology demo here at the IEEE Standards...
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CDNLive Israel: Optimizing SoC Design in Data-Rich Applications
The Cadence Tensilica team traveled to Tel Aviv to host a special processor-technology focused track at CDNLive Israel (Nov. 3). It’s a region long known for IP, DSP, and SoC startup development as...
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