Low-power design for electronic systems has made significant progress, but there are still disconnects at the software and architectural levels, according to panelists at the Low-Power Technology Summit held at Cadence San Jose headquarters Nov. 18. The lively discussion also sparked disagreements about analog/mixed-signal scaling and asynchronous design. The panel was titled “ Health Check-Up for Your Low-Power Design ,” and it followed a day-long series of customer and Cadence presentations, including one presentation from each of the four panelists. These presentations are available online . The panelists were as follows, shown left to right in the photo below. Elad Alon – Associate Professor of Electrical Engineering and Computer Science at U.C. Berkeley and Co-Director of the Berkeley Wireless Research Center (BWRC) David Flynn – R&D Fellow in the Silicon Group at ARM John Redmond – Associate Technical Director at Broadcom’s Broadband Connectivity Group Kenneth Wagner – VP, Communications Products Division, PMC Sierra The panel was conducted in a question-and-answer format. Here are some of the highlights, starting with an opening question from moderator Brian Fuller, editor in chief at Cadence: Q: What’s your prescription for low-power design? Are we making progress or still chasing our tails? Alon: I think the number one prescription is to pay attention to everything around you. Often times the best knobs to turn are not in the block you defined. A lot of problems come when we’re not really paying attention to the overall system. Flynn: We’ve got to get better hooks back to the software developers at the application level. I think it's happening. Redmond: I’ll give us a B-minus in terms of tools and flows. We’ve solved a lot of the leakage problems but there are still a lot of struggles on the dynamic power side. The reason I give it a B minus is that a lot of people have just taken the low hanging fruit. There is a lot more work to be done. Wagner : For implementation, I would credit the EDA vendors with more than a B minus. We could probably derive an A minus in that area. The place where we’re lagging is on the architectural side. We have to continue to put pressure on the architectural level and be flexible. We’re starting to see people dabble in asynchronous design. Q: As humans, we always underestimate or overestimate various challenges. What are we underestimating now and what will we overcome more easily than what people think? Alon: Many of the issues we run into really come back to complexity. We keep trying to integrate more and more functionality. We’re not scaling at the same rate, at least not from sheer transistor count. Designers need to be able to think more holistically. Flynn: If we’re going to have 40 to 50 billion connected devices, are we going to change 40 to 50 billion batteries? I think we have underestimated how to power all this stuff efficiently. Redmond: I think we’re underestimating the run-ime decisions. I think we’re going pretty well with design time decisions, but at runtime it’s basically, “you’re not using that thing, so shut it off.” One thing we might be overestimating is dark silicon. I think engineers will solve that issue. Wagner: One area I think we’re underestimating is energy modeling at the system level. We need to work on standards at the system level. The IEEE has two new standards bodies working on this. [Note: See previous blog post for details]. Q: We’ve done all this work on chips and the software guys don’t take advantage of it. Could that be because there’s too much inside of the box, and we’re developing the wrong knobs? Redmond: That could be part of the issue. One promising development is IEEE 2415, which is trying to bridge the gap between hardware and software. If we can get some standardization so the software can understand the hardware, things will be better. Alon: If you look at the success Apple has, it’s because they are vertically integrated. There is less of an artificial boundary between the applications guy and the software guy, and they tend to have much better final solutions. A lot of this is all about getting the right people in the room. Q: How well are today’s compilers taking advantage of hardware power management features? Alon: From a purely academic side, there are compiler techniques that do a reasonable job, but many of these are specifically linked to a particular hardware architecture. There is no one unified architecture for general processing. There are certain classes of applications that require various computation styles. Q: The industry has put a lot of time and effort into low power for digital. What about analog/mixed-signal? Wagner: If you look at the IP vendors, there is a great deal more sensitivity these days and power is optimized. We see power optimized versions of SerDes and other types of mixed-signal designs. I think one problem is that mixed-signal has not benefited as much by going to new process nodes. Alon: If I may inject some controversy, if you look at analog-to-digital converters, they have actually scaled faster than digital circuits. They are benefiting from many of the same things from a technology standpoint. There are things in the mixed-signal domain that are constrained by thermal noise or dynamic range, and here scaling doesn’t buy anything. But most of the [analog/mixed-signal] stuff you probably work with should scale as well as digital, if not sometimes a little better. Wagner: I disagree. We’re running out of headroom much more quickly at advanced nodes. Flynn: I’ve been working with some wizened analog engineers and they say stuff doesn’t scale anymore at all. Q: What’s next for low-power design on the chip side? I haven’t seen anything new for 5 years. Wagner: I disagree we’ve been stagnant for 5 years. There have been improvements in both the static and dynamic areas. One problem is that we don’t talk about the latest techniques – they are proprietary. Q: Asynchronous design has power advantages, but there are a lot of obstacles. Will it ever be a reality? Wagner: It’s a reality today in areas where security is an issue. Asynchronous processors tend to be power efficient, performance inefficient, and area inefficient. Alon: I would challenge the statement that asynchronous is lower power. You’re solving the same problem – you’re just distributing it among all your stages instead of centralizing it. There are instances where it is more efficient, but in many areas it’s actually less efficient. Flynn: I’ve seen quite good asynchronous designs, but designers always struggle with asynchronous verification. Presentations Given by Low-Power Panelists The following presentations were given before the panel discussion and are available online: Elad Alon – Realizing Energy-Efficient SoCs Demands Vertically Integrated Design(ers) (Highlights from Alon's talk are also online .) David Flynn – Design Challenges in Developing Sub-Volt IP Designs for IoT Applications John Redmond – Thriving in a Multi-Vendor Interoperable IEEE 1801 Low-Power Design Flow Kenneth Wagner – Power Estimation – An Evolving Science Richard Goering Related Blog Posts IEEE Working Groups Open New Frontiers in Low Power Design Designer View – Getting the Best Use from Static Low-Power Verification![]()
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