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TSMC Technology Symposium Preview: Note New Location!
Before I go any further, after years and years of being at the San Jose Convention Center, this year's TSMC Technology Symposium has moved. It will be in the Santa Clara Convention Center. And, while...
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Virtuosity: What's New in Run plan – Part I
The Run Plan assistant in Virtuoso® ADE Assembler has proved to be one of the most popular features. It provides the capability to create multiple variations of the setup within a single session, each...
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ISPD18 Contest and Cadence Academic Network Cloud Solutions
ISPD is the International Symposium on Physical Design. The ISPD contest is a well-known competition in EDA field, where the main idea is to have EDA companies sharing the industrial problems they are...
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Linley: Training in the Datacenter, Inference at the Edge
In mid-April I was at the Linley Processor Conference. As usual, Linley Gwennap gave the opening keynote. He titled it How Well Does Your Processor Support AI? which was the perfect straight man...
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Tech Blog Series: Sensitivity Analysis+Optimization — Now That's Formidable!
Anyone who designs complex circuits and claims they don’t use the Optimizer on their design is most likely a super-genius with an IQ of 250. Sure, most of you have used the Optimizer on your circuit...
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What's For Breakfast? Video Preview April 30th to May 4th 2018
https://youtu.be/Zpui6QhXM_o Coming from The San Jose Tech Museum (camera Sean) Monday: AMI for DDR5 Tuesday: TSMC related embargoed announcement Wednesday: TSMC related announcement Thursday: TSMC...
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SI Methodology for Multi-Gigabit Serial Link Interfaces (8 of 8)
Automated Compliance Checking With detailed post-layout interconnect in place, and the IBIS-AMI models properly executing, attention can turn to compliance checking for the specific interface of...
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Why the Future of Electrical Engineering is in Peril
I was looking around at CDNLive a couple of weeks ago, and something struck me about the demographics of the people that were there. You can guess, of course, that they were mostly male, and of diverse...
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Whiteboard Wednesdays - Automotive Sensors: Concepts and Trends
In this week’s Whiteboard Wednesdays video, the second in a three-part series, Robert Schweiger does a deep dive on the technical aspects of the different sensors on a car: camera, radar, and lidar....
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RSA Cryptographers' Panel
The RSA Conference is the biggest conference in security. This year there are 50,000 attendees. Yes, security is on everyone's radar, finally. It is in the Moscone center, in all of North, South, and...
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5 Reasons to Submit an Abstract for CDNLive India
Call for Presentations (CFP) for CDNLive India is now open! While this is something that I get excited about every year, I thought it would be a good idea to highlight some of the reasons why you...
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Qualcomm and Arm Drink Their Own Champagne
Everyone in EDA is familiar with the phenomenon where the internal testing of a tool all goes perfectly, the initial customer checkout flights of the tool go well. Then when that same customer starts...
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Some Real Russian Hacking
Patrick Wardle and Mikhail Sosonkin were in Moscow for a PHDays (positive hacking). Gianna Toboni of HBO's VICE News was there too, shooting an episode. The program reached out and asked, "Can you hack...
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Virtuoso IC6.1.7 ISR19 and ICADV12.3 ISR19 Now Available
The IC6.1.7 ISR19 and ICADV12.3 ISR19 production releases are now available for download at Cadence Downloads . IC6.1.7 ISR19 ICADV12.3 ISR19 For information on supported platforms, compatibility with...
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Reduce Time-to-Market for Your System-level Designs Using PSpice Systems Option
I was reading an autobiographical narrative by Kenneth Anderson (1910 – 74), a renowned Indian wildlife expert of Scottish descent. Now, Mr. Anderson was also an automobile enthusiast – loved toying...
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AMI for DDR5 Made Easy
In a post last week, I covered IBIS and AMI. One big change that is happening is that the DDR5 standard will (indirectly) mandate using AMI models. DDR5 In the DDR5 standard, which is expected to be...
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Virtuosity: Use Colin Thomson's New RAK to Learn How Legacy Designs Can be...
Layout XL-Compliance Rings a bell? If it does, you're at the right place, well page! If it doesn't, you're certainly at the right page. For those of us who are familiar with the sound of Layout...
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WoW! TSMC Sticks Whole Wafers Together
Today it is the TSMC Technology Symposium. As always, Cadence is making several announcements jointly with TSMC. 5nm and 7nm+ This isn't the biggest surprise announcement of the year. Cadence is...
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Whiteboard Wednesdays - Tensilica DSPs, Sensors, and Neural Networks
In this week’s Whiteboard Wednesdays video, the last in a three-part series, Robert Schweiger closes the loop on the advantages of hybrid sensor fusion platforms in combination with smart sensors....
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DDR5 IP Test Chip Operates with Micron Prototype DRAM at 4400 MT/s
The DDR5 standard has not been finalized by JEDEC, and they are very strict about not allowing anyone to claim DDR5 compatibility until the standard is complete. That is expected sometime this summer....
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