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Indian Airports Go High Tech
No more printed tickets. Shorter queues at check-in counters. Humanoid robots walking amidst you, giving you directions and guidance. Get ready for all this and more in just a few months from now....
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Imec Roadmap
I recently visited imec. For an overview of my day, see my earlier post If It's Tuesday This Must Be Belgium. My First Visit to imec . One of the things that imec does is to take the funnel of...
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Speedup SystemVerilog UVM Debug Regression Time with Dynamic Test Load
Microsemi has been evaluating a unique feature in Xcelium System Verilog UVM Dynamic Test Load for some time now, and they shared their thoughts on it in a paper presented at CDNLive San Jose April...
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Virtuoso IC6.1.7 ISR20 and ICADV12.3 ISR20 Now Available
The IC6.1.7 ISR20 and ICADV12.3 ISR20 production releases are now available for download at Cadence Downloads . IC6.1.7 ISR20 ICADV12.3 ISR20 For information on supported platforms, compatibility with...
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Why Did EDA Have a Hardware Business Model?
Business models are really important. Just ask any internet startup company that has lots of users and is trying to work out how to monetize them. It is a lot easier to get people to use something for...
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Virtuosity: Let's Have Fun with ADE Debugging – Part 1
How to debug job distribution issues in ADE? Long, long time ago, there was a tool named Analog Artist. If you have been around long enough to have used that tool, then welcome to our club, old timer!...
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FD-SOI vs FinFET: Dan Hutcheson Re-Runs His Survey
Recently, the SOI Consortium held its annual Silicon Valley Symposium. I was only able to attend in the afternoon since I spend the morning at the ESD Alliance workshop on digital marketing (for more...
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DMS 2.0 - What's Cool and What's New
Are you aware of all the cool new features in Digital Mixed Signal 2.0 (DMS 2.0)? Provided with the Xcelium Parallel Simulator versions 17.10 and beyond, DMS 2.0 brings you all kinds of new and...
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What's For Breakfast? Video Preview June 18th to 22nd 2018
https://youtu.be/jm8EGgpzF_A Coming from Dilijian Armenia (camera Gary Bengier) Monday: Why Millennial Engineers Should Work for Cadence Tuesday: Wrapup from the RSA Security Conference Wednesday:...
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Imec on EUV. Are We There Yet?
I already gave an introduction to my first visit to imec in my life in my post If It's Tuesday This Must Be Belgium. My First Visit to imec One of the things I mentioned there is that they have an EUV...
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High-Level Synthesis: The Secret Is Out
Gone is the day when companies (our customers) kept their use of high-level synthesis (HLS) quiet, a secret advantage over their competitors. As HLS usage became more widespread, the secret is out ,...
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Cadence Puts the IP in ...well, IP
A lot has been written about AI and machinelearningdeeplearning, but a friend asked me, what does that have to do with Cadence, anyway? And what do you mean when you say, IP? I realized that I haven’t...
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Whiteboard Wednesdays - What Really Matters When Selecting IP
In this week’s Whiteboard Wednesday, Tom Hackett says that PPA is only the tip of the iceberg of requirements to consider when selecting IP for your next chip design. https://youtu.be/2S6V5RpXECM
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"I Couldn't Imagine Being Too Poor for Servants, or Rich Enough for a Car"
Agatha Christie, looking back on her early life, remarked that she: I couldn’t imagine being too poor to afford servants, nor so rich as to be able to afford a car. Like most of us, I've been the other...
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30 Year of Innovation - And There’s Still So Much to Do!
Last week I captured the highlights of the progress we’ve made in the past 30 years in the blog post, 30 Years of Innovation – We’ve come so far. And while I’ve witnessed a lot of these changes over...
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What Is COM /JCOM Channel Compliance All About?
In today’s world of double-digit gigabit-per-second data rates it is imperative that engineers properly design and characterize their system to meet standards compliance. This sounds simple enough but...
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Pie and Chips at DAC: ChipEstimate.com and the First Annual Pi Contest
In Scotland, there is a traditional dish of pie and chips. But the pie is not a sweet fruit pie, like something Marie Callendar would make, but it is full of minced lamb. And chips are what Americans...
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The Design Infrastructure Alley
One of the new things at DAC this year is the Design Infrastructure Alley. The Alley is an initiative from the ESD Alliance and the Association for High-Performance Computing Professionals to highlight...
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Is it Time to Verify Your Chips in the Cloud? Part 1 of 3
Welcome to the first installment of a three-part blog series examining the issues and opportunities for performing verification in the cloud. For a while now, there’s been a growing interest in...
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Academic Track at CDNLive EMEA 2018
From 7-9.05 the CDNLive circus made it stop in Munich / Germany for full three days. For Academic Network in EMEA this is the most important event through the year, as we are organizing the Academic...
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