IEDM: Embedded Memories
On the Sunday of IEDM are two short courses, one memory-focused, and one logic-focused. I always attend the logic one since that is more relevant to the broad semiconductor industry and to EDA in... [[...
View ArticleNew Training Bytes Available Now: All About SystemVerilog Classes
If you’re leaving 2018 with the feeling that your SystemVerilog skills are lacking, don’t worry—there’s a new series of Cadence Training Bytes to help you hit the ground running in 2019. Here you’ll......
View ArticleEmpowered to Support Our Community
Cadence understands that the success of our business, our employees, and the community are fundamentally tied together. As part of creating a strong work environment and reinforcing our One... [[ Click...
View ArticleVirtuosity: Introducing the Pin Tool
Overview Going out for dinner? You really wouldn’t want to buy the appetizer from one restaurant, the main course from another, and the dessert from a third one. It’s great to have everything under......
View ArticleCES: 5G, All Hat and No Cattle
Increasingly, CES seems to be less about consumer electronics, and more about the big tectonic shifts in technology. Indeed, CES is no longer the Consumer Electronics Show, it is just CES. Of...
View ArticleSpecman is Sweet – Bosch Sensortec's Story
Recently, Bosch Sensortec has been using Specman for their functional verification needs in their Inertial Measurement Unit, and they’re loving it. Why is Specman so cool? Well, it’s implementing...
View ArticlePersistent Memory
Last week was the latest Persistent Memory Summit. In the semiconductor world, we don't usually use that word, we say non-volatile memory. In practice, this mostly means flash memory (mainly 3D... [[...
View ArticleWhat Next for Modus DFT?
I sometimes say that test is the red-headed stepchild of EDA, that doesn't get the same glory as the more high profile parts of the EDA flow such as synthesis, or place & route, or signoff.... [[...
View ArticleVirtuosity: Simulation Planning and Coverage Environment (SPACE)- Introduction
Complexity in Analog designs is increasing rapidly as technology is shrinking beyond 28 nanometers. Such complexity leads to a huge list of operating conditions ( Process , Voltages and Temperatures......
View ArticleProgramming Persistent Memory
I talked earlier this week about the recent persistent memory summit (see my post Persistent Memory ). If DRAM gets faster or higher capacity, then there isn't anything that software engineers... [[...
View ArticleSunday Brunch Video for 3rd February 2019
https://youtu.be/CXTltDRjb-M Made at DesignCon 2019 (camera Sean) Monday: IEDM: Embedded Memories Tuesday: CES: 5G, All Hat and No Cattle Wednesday: Persistent Memory Thursday: What Next for Modus......
View ArticleDesignCon: Cadence Teaches AMI and IBIS
At the recent DesignCon, Cadence and customer IBM presented a tutorial on Advanced IBIS-AMI Techniques for 32 GT/s and Beyond . If you are not well-versed in SerDes and signal integrity, your first......
View ArticleEmerging Memories Poised to Explode
A couple of weeks ago was the Persistent Memory Summit. (For more details, see my post Persistent Memory .) Normally, this might be a minority-interest event, but the potential arrival of a new...
View ArticleDesignCon 2019
It doesn't seem to matter what a show is ostensibly about at the moment. Every show seems to be talk about quantum computing, 5G or Artificial Intelligence. DesignCon, the focus of which is PCB... [[...
View ArticleVirtuoso IC6.1.8 ISR1 and ICADVM18.1 ISR1 Now Available
The IC6.1.8 ISR1 and ICADVM18.1 ISR1 production releases are now available for download at Cadence Downloads . IC6.1.8 ISR1 ICADVM18.1 ISR1 For information on supported platforms, compatibility with......
View Article60 Years of DARPA—61 Actually
On 4th August 1957, the Soviet Union launched the first artificial satellite, Sputnik 1 ("sputnik" means "satellite" in Russian). It wasn't very impressive by modern... [[ Click on the title to access...
View ArticleVirtuoso ADE Verifier in IC6.1.8 and ICADVM18.1 – Better, Faster, Further!
Cutting-edge innovation … Top-down planning … Reliable and formalized verification … Scalable performance ! These are the current buzzwords floating around in the electronic design automation... [[...
View ArticleSimulation for a Song: Downloading Models from the Web and Associating with...
While on a long drive, I like to sing along; say Eye of the Tiger or Johny B Goode or Sweet Home Alabama (even though I don’t live in Alabama), the music being an active part of the journey,... [[...
View ArticleBreak the Wall! Merging Circuit Design Flow and Layout Design Flow for FinFET...
The FinFET device architecture, which is currently a major trend in advanced node process technologies, has advantages such as high drivability and low leakage current. However, it has significant......
View ArticleWill Crypto Change the World?
Do you remember when you had to pay for ringtones? In 2005, analysts were predicting that ringtones would be a $10+B market by 2010. In that pre-smartphone era, you could only install a ringtone if......
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