Virtuoso IC6.1.8 ISR3 and ICADVM18.1 ISR3 Now Available
The IC6.1.8 ISR3 and ICADVM18.1 ISR3 production releases are now available for download at Cadence Downloads . IC6.1.8 ISR3 ICADVM18.1 ISR3 For information on supported platforms, compatibility with......
View ArticleVirtuoso Video Diary: Creating and Previewing Stimuli
Over the next few weeks, the Virtuosity and Virtuoso Video Diary blogs will focus on the just-released features in Virtuoso®ADE Assembler , Virtuoso®ADE Explorer , and Virtuoso®... [[ Click on the...
View ArticleSpectre Tech Tips: Measuring Noise in Digital Circuits
As a designer, verification engineer, or CAD expert, you use Spectre® APS for analyzing your designs. Sometimes, you use Spectre to measure noise in digital circuits. Are you confused which... [[ Click...
View ArticleWhat’s the Buzz About Bees and Tech?
Recently, a friend of mine discovered a swarm of bees on his property. He called a local beekeeper, who came to capture the bees and take them to a safe, new hive. While she was working, she talked......
View ArticleWhiteboard Wednesdays - SIMD Capability of B10 B20 and Some Associated Vector...
In this week's Whiteboard Wednesdays video, Pierre-Xavier Thomas shows some of the processing units of the B10/B20 supporting the SIMD architecture in the context of the operator support.... [[ Click...
View ArticleLinley Gwennap's Deep Dive into Deep Learning
At the recent Linley Spring Microprocessor Conference, Linley Gwennap kicked off with the opening keynote on what is clearly the biggest thing to hit processors in a long time: deep learning. Linley......
View ArticleCadence at the HOST Symposium: Come See What We're Doing!
The HOST Symposium is returning for its 12 th year, and general registration is open now. The IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) aims to accelerate and...
View ArticleCadence at the Red Hat Summit--Come See Xcelium in Action!
The Red Hat Summit is coming around to Boston this year, and it’s only a few short days away. Cadence has a demo at the Marvell booth (that’s #418-1), and we’ll be there from 3-7 PM on Wednesday,...
View ArticleTSMC: Specialty Technologies
What is a "specialty technology"? Kevin Zhang, the VP of business development, told us at the recent TSMC Technology Symposium: If Yuh-Jier Mii doesn't talk about it, then it's a... [[ Click on the...
View ArticleVirtuosity: Filtering Plots!
Over the next few weeks, the Virtuosity and Virtuoso Video Diary blogs will focus on the just-released features in Virtuoso®ADE Assembler , Virtuoso®ADE Explorer , and Virtuoso®... [[ Click on the...
View ArticleTSMC: Zero Excursion, Zero Defect
At the recent TSMC Technology Symposium, JK Wang, the SVP of fab operations, talked about Manufacturing Excellence . There were two parts to this: Capacity ramping and new fab status The pursuit of......
View ArticleBoardSurfers: Make Menus Your Own – Customizing Menus and Toolbars with...
Flexibility and the ability to customize the software/environment to your own personal needs is a definite strength of Cadence® software, and the Allegro® platform is no different. Whether... [[ Click...
View ArticleSunday Brunch Video for 5th May 2019
https://youtu.be/ICpG3ouDIyQ Made at Nathan's Tesla (camera Sean) Monday: Andy Bechtolsheim: 85 Slides in 25 Minutes, Even the Keynote Went at 400Gbps Tuesday: Tesla Drives into Chip Design... [[ Click...
View ArticleA new Electrostatic Discharge Analysis Solution – You Will Never Get Zapped!
“ It’s not what it is, it’s about what it can become ” -The Lorax by Dr. Seuss Have you recently reached out to open your car and received an unexpected shock…zap! There are no financial or health......
View ArticleStatistical Power...or Why You Shouldn't Be Allowed to Turn Right on Red
I wrote last Friday in my post TSMC: Zero Excursion, Zero Defect about the statistical processes that are essential in semiconductor manufacturing to get high yield, and to catch any issues that... [[...
View ArticleVirtuoso Video Diary: What's New in Reliability Setup
Today's blog highlights the enhancements made to the Reliability Options form and to the overall reliability setup. This blog is a part of the mini blog series that we are posting twice a... [[ Click...
View ArticleJasperGold: the Next Generation
Formal verification has gone through a number of eras. In the early 1990s, it was an area mostly of academic interest, only able to handle toy problems. Then, in 1994, was the infamous FDIV bug. As......
View ArticleA Special Day for Cadence India
A few days ago, Cadence Bangalore, Noida and Pune sites had the opportunity to participate in a worldwide CSR initiative in collaboration with the NGO Rise Against Hunger (RAH). To celebrate our...
View ArticleWhiteboard Wednesdays - Limitations of Scan Compression QoR
In this week's Whiteboard Wednesdays video, Scan Compression reduces the digital IC test time and data volume by orders of magnitude, but the technology’s limitations prevent achieving higher... [[...
View ArticleHow Do Out-of-Order Processors Work Anyway?
I've been meaning to write a post on how out-of-order processors work, but one challenge is to make the diagrams that are necessary to make it clear. Well, Jon Masters of Red Hat gave the keynote... [[...
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